Oldest pages

Jump to navigation Jump to search

Showing below up to 129 results in range #21 to #149.

View (previous 250 | next 250) (20 | 50 | 100 | 250 | 500)

  1. Mixed-signal system modelling and simulation‏‎ (17:30, 16 July 2019)
  2. Ngspice - an open source mixed signal circuit simulator‏‎ (17:34, 16 July 2019)
  3. Gnu Circuit Analysis Package (GnuCap)‏‎ (17:35, 16 July 2019)
  4. GnuCap: Progress and Opportunities‏‎ (17:36, 16 July 2019)
  5. Open Source in Healthcare, an hardware approach: the echOpen project case‏‎ (17:37, 16 July 2019)
  6. ASICone. Goals, timeline, participants and tools‏‎ (17:39, 16 July 2019)
  7. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon‏‎ (17:40, 16 July 2019)
  8. CMP add on services - Towards Foundry PDKs on Free CAD Tools‏‎ (17:43, 16 July 2019)
  9. Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes‏‎ (17:44, 16 July 2019)
  10. Converting 45nm transistor netlists to open standards‏‎ (17:45, 16 July 2019)
  11. The development of the NSXLIB standard cell scalable library‏‎ (17:46, 16 July 2019)
  12. OpenRAM: An Open-Source Memory Compiler‏‎ (17:48, 16 July 2019)
  13. FOS standard cell generator from scratch‏‎ (17:51, 16 July 2019)
  14. Placement algorithms for standard cells in Coriolis‏‎ (17:52, 16 July 2019)
  15. KLayout's deep verification base project‏‎ (17:55, 16 July 2019)
  16. CMOS functional abstraction‏‎ (17:57, 16 July 2019)
  17. Open Source Parasitic Extraction‏‎ (17:58, 16 July 2019)
  18. CERN OHL v2 draft‏‎ (18:02, 16 July 2019)
  19. Toward a collaborative environment for Open Hardware Design‏‎ (18:04, 16 July 2019)
  20. High level system modelling, hands-on computer session‏‎ (18:05, 16 July 2019)
  21. From filters to CMOS transistors - A library of analog schematics with automated sizing‏‎ (18:06, 16 July 2019)
  22. ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals‏‎ (18:08, 16 July 2019)
  23. The Alliance/Coriolis design flow‏‎ (18:10, 16 July 2019)
  24. Hands-on with KLayout: Design rule checks and layout to netlist tools‏‎ (18:11, 16 July 2019)
  25. The Raven chip: First-time silicon success with qflow and efabless‏‎ (01:06, 12 November 2019)
  26. Matthias:UnsortedThroughsOnFOSSForEDA‏‎ (14:45, 24 January 2020)
  27. White paper for the EC, January 2020‏‎ (16:49, 3 February 2020)
  28. Need for a free alternative to OpenAccess (by Matthias)‏‎ (22:23, 14 February 2020)
  29. LibrEDA‏‎ (23:54, 12 January 2021)
  30. Standard-cell recognition‏‎ (23:09, 16 February 2021)
  31. Standard-cell characterization‏‎ (18:36, 21 May 2021)
  32. F-Si Statute‏‎ (23:50, 22 December 2021)
  33. FSiC2021‏‎ (12:27, 7 February 2022)
  34. FSiC2020‏‎ (12:28, 7 February 2022)
  35. KiCad‏‎ (15:58, 10 March 2022)
  36. Horizon 2021 Coordination and Support Action (CSA) proposal‏‎ (12:05, 17 June 2022)
  37. F-Si Donations‏‎ (09:41, 23 June 2022)
  38. FSiC2022 venue‏‎ (13:46, 6 July 2022)
  39. XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design‏‎ (12:22, 12 July 2022)
  40. Composing an out-of-order CPU using software technics‏‎ (22:26, 1 August 2022)
  41. Inclusive Modeling with SysMD‏‎ (22:29, 1 August 2022)
  42. Wishbone: a free SoC bus family‏‎ (22:29, 1 August 2022)
  43. Porting software to hardware using XLS and open source PDKs‏‎ (22:31, 1 August 2022)
  44. Synthesis with ghdl‏‎ (22:32, 1 August 2022)
  45. How many designs can you fit on a single die‏‎ (22:33, 1 August 2022)
  46. Standard Cell Library report‏‎ (22:34, 1 August 2022)
  47. Go2async: A high-level synthesis tool for asynchronous circuits‏‎ (22:36, 1 August 2022)
  48. KLayout XSection tool - Deep insights or nonsense in colors?‏‎ (22:37, 1 August 2022)
  49. OpenSource PDK - A key enabler to unlock the potential of an open source design flow‏‎ (22:38, 1 August 2022)
  50. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries‏‎ (22:40, 1 August 2022)
  51. Challenge to Fabricate LSI without NDA with Open Method‏‎ (22:42, 1 August 2022)
  52. F8‏‎ (22:47, 1 August 2022)
  53. OpenEPDA: photonic PDKs with open standards‏‎ (22:56, 1 August 2022)
  54. Merging Gnucap and Qucs -- The Why and How‏‎ (22:59, 1 August 2022)
  55. Whom do you trust?: Validating process parameters for open-source tools‏‎ (23:00, 1 August 2022)
  56. LibrEDA - digital place-and-route framework from scratch‏‎ (23:00, 1 August 2022)
  57. Digital placement algorithms in Coriolis‏‎ (23:01, 1 August 2022)
  58. Naja: an open source framework for EDA post synthesis flow development‏‎ (23:02, 1 August 2022)
  59. Tutorial and FAQ on physical verification, DRC+LVS‏‎ (23:05, 1 August 2022)
  60. 65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview‏‎ (11:16, 23 August 2022)
  61. Wiki/openic‏‎ (04:02, 4 September 2022)
  62. LibreCell‏‎ (00:34, 16 December 2022)
  63. Standard-cell synthesis‏‎ (15:48, 2 February 2023)
  64. FSiC2023 venue‏‎ (15:12, 2 July 2023)
  65. TestPageX‏‎ (14:14, 8 July 2023)
  66. Naja: project updates and netlist splitting tool‏‎ (22:32, 9 July 2023)
  67. E-Waste Reverse Engineering Toolkit (RET)‏‎ (00:05, 11 July 2023)
  68. Software-Defined Hardware: Digital Design in the 21st Century with Chisel‏‎ (22:13, 28 July 2023)
  69. A progressive introduction to memory bus interconnect API in Software-Defined Hardware‏‎ (22:14, 28 July 2023)
  70. Mixing software abstractions for high-level FPGA programming‏‎ (22:14, 28 July 2023)
  71. Toward multi-language open-source HDL simulation‏‎ (22:15, 28 July 2023)
  72. Recent Developments from YosysHQ‏‎ (22:15, 28 July 2023)
  73. Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry?‏‎ (22:16, 28 July 2023)
  74. Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana‏‎ (22:16, 28 July 2023)
  75. Proof-of-concept for scalable analog blocks using the PDKMaster framework‏‎ (22:16, 28 July 2023)
  76. Open source Design Flow status and roadmap for IHP BiCMOS technology‏‎ (22:17, 28 July 2023)
  77. TinyTapeout - what happened and next steps‏‎ (22:18, 28 July 2023)
  78. Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites‏‎ (22:18, 28 July 2023)
  79. Analyzing open-source chip design ecosystem from an environmental sustainability perspective‏‎ (22:19, 28 July 2023)
  80. Open Source for Sustainable and Long lasting Phones‏‎ (22:19, 28 July 2023)
  81. Open-source electronic design automation for agile network defense at OVHcloud‏‎ (22:20, 28 July 2023)
  82. Physical security for cryptographic implementations with open hardware‏‎ (22:20, 28 July 2023)
  83. Black-tie Python: Formal verification with Amaranth‏‎ (22:21, 28 July 2023)
  84. Exploring open hardware solutions for ensuring the security of RISC-V processors‏‎ (22:21, 28 July 2023)
  85. A Yosys plugin for logic locking‏‎ (22:22, 28 July 2023)
  86. All you ever wanted to know about side-channel attacks and protections (and a forthcoming book)‏‎ (22:22, 28 July 2023)
  87. Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology‏‎ (22:22, 28 July 2023)
  88. Verilog-AMS in Gnucap‏‎ (22:23, 28 July 2023)
  89. How to foster GreenIT through open hardware?‏‎ (22:24, 28 July 2023)
  90. The importance of EU Academia in developing the chips of the future‏‎ (22:25, 28 July 2023)
  91. Open (and Closed) Source Analog Design with Hdl21 & VLSIR‏‎ (22:26, 28 July 2023)
  92. An overview of libre silicon and OSHW related efforts within NGI and NLnet‏‎ (22:27, 28 July 2023)
  93. KQCircuits – open-source EDA software for designing chips with super conducting qubits‏‎ (22:28, 28 July 2023)
  94. Coriolis a RTL to GDSII FOSS Design Flow‏‎ (22:28, 28 July 2023)
  95. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks‏‎ (22:29, 28 July 2023)
  96. Teaching Chip Design with Open-Source Tools‏‎ (22:29, 28 July 2023)
  97. Learning hardware design in the video game Minecraft‏‎ (22:29, 28 July 2023)
  98. Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks‏‎ (22:29, 28 July 2023)
  99. OpenROAD‏‎ (12:09, 11 August 2023)
  100. The road to fully open hardware mobile computing‏‎ (15:08, 24 August 2023)
  101. Introduction to the GoIT project‏‎ (15:11, 24 August 2023)
  102. Welcome from LIP6‏‎ (16:23, 24 August 2023)
  103. Welcome from the Free Silicon Foundation 2023‏‎ (16:24, 24 August 2023)
  104. Recommendations for the EC on how to reduce the environmental impact of the ICT sector‏‎ (22:10, 30 September 2023)
  105. FSiC2023‏‎ (17:08, 1 October 2023)
  106. FSiC2022‏‎ (17:09, 1 October 2023)
  107. FSiC2019‏‎ (17:09, 1 October 2023)
  108. Environmental impacts of electronics and the role of open source hardware‏‎ (16:34, 20 October 2023)
  109. Recommendations and roadmap for the development of open-source silicon in the EU‏‎ (19:13, 3 November 2023)
  110. Main Page‏‎ (17:24, 25 January 2024)
  111. Free Silicon Foundation‏‎ (14:57, 31 January 2024)
  112. Gdsfactory‏‎ (11:21, 6 March 2024)
  113. Statute of the Free Silicon Foundation (I) ETS‏‎ (17:47, 28 March 2024)
  114. FSiC2024 venue‏‎ (17:29, 22 April 2024)
  115. Guidelines for speakers‏‎ (19:17, 22 April 2024)
  116. Revolutionize your chip design with GDSFactory and Open Source PDKs‏‎ (20:49, 22 April 2024)
  117. Verilog-A Circuit Analysis Kernel (VACASK)‏‎ (08:54, 23 April 2024)
  118. The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies‏‎ (09:04, 23 April 2024)
  119. Degate: The stakes and challenges of silicon reverse engineering‏‎ (19:32, 23 April 2024)
  120. From Theory to Tape-Out: Chip Design Education with Edu4Chip‏‎ (15:04, 24 April 2024)
  121. The ACT EDA flow for asynchronous logic‏‎ (17:08, 24 April 2024)
  122. VACASK: a Verilog-A Circuit Analysis Kernel‏‎ (15:35, 25 April 2024)
  123. Verilog-AMS in Gnucap (2024)‏‎ (16:09, 25 April 2024)
  124. Caravel Panamax: The Next Generation‏‎ (22:19, 30 April 2024)
  125. CACE: Defining an open-source analog and mixed-signal design flow‏‎ (22:29, 30 April 2024)
  126. An opensource Wi-Fi chip, What, Why and How?‏‎ (09:32, 2 May 2024)
  127. Moving toward VexiiRiscv‏‎ (23:39, 2 May 2024)
  128. Generating DRC Runsets for IHP's OpenPDK - Lessons Learned‏‎ (13:39, 3 May 2024)
  129. FSiC2024‏‎ (19:10, 5 May 2024)

View (previous 250 | next 250) (20 | 50 | 100 | 250 | 500)

Retrieved from "https://wiki.f-si.org/index.php?title=Special:AncientPages"