Toward multi-language open-source HDL simulation
- Speaker(s): Tristan Gingold
- email: Tristan Gingold
GHDL was first a compiled VHDL simulator. It was later extended to support synthesis, either standalone and generating a simple vhdl or verilog netlist), or as a plugin for yosys. Recently a limited support of verilog has been added in order to improve the support of mixed-language design synthesis. The rules to mix designs are discussed in this presentation.
- The project seeks help on: AMS