Toward multi-language open-source HDL simulation

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  • Speaker(s): Tristan Gingold
  • email: Tristan Gingold



GHDL was first a compiled VHDL simulator. It was later extended to support synthesis, either standalone and generating a simple vhdl or verilog netlist), or as a plugin for yosys. Recently a limited support of verilog has been added in order to improve the support of mixed-language design synthesis. The rules to mix designs are discussed in this presentation.


General information


  • The project seeks help on: AMS