A progressive introduction to memory bus interconnect API in Software-Defined Hardware

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  • Speaker(s): Charles Papon
  • email: charles.papon.90@gmail.com
  • other information: Dolu1990 (Github)



This talk will introduce differents API and paradigmes which can be used to specify an interconnect in software-defined hardware.

It will do so by showing some regular interconnects from the SpinalHDL library, before diving in some recent developpment mixing Tilelink, parameter negotiation, Multithreaded and decentralized hardware elaboration.


General information


  • Tilelink infrastructure with memory coherency (With and without L2)
  • SMP SoC with NaxRiscv