Standard-cell synthesis

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Standard-cell synthesis describes the process of creating the physical layout of a standard-cell based on some more abstract description such as a transistor level netlist or a boolean function.


Standard-cells are usually the basic building blocks of digital integrated circuits. This includes logic (boolean) functions (such as INV, NAND, NOR), multiplexers, tri-state cells, state holding elements (Flip-Flops, Latches) and some special cells that don't contribute to the logic functionality of the circuit but are necessary for physical reasons or due to the fabrication process (tie cells, MOS capacitors, antenna diodes, CMP fill).

Essentially, the layout of a standard-cell contains placed and routed transistors that implement the desired logic function. Therefore standard-cell synthesis is all about placing and routing transistors.

Layout Styles

CMOS standard cell layout styles

Layout synthesis is strongly influenced by assumptions about the layout and the technology. Some of the common assumptions are:

  • 2-stack cell.
    • Transistors are strictly put onto two rows between the power rails. Often one row is reserved for N-FETs, the other for P-FETs (a).
  • Strict separation of transistors by channel type.
    • a) Usual in bulk CMOS to avoid latch-up.
    • b) SOI allows to mix channel types.
  • c) Gate orientation.
    • More advanced technologies require all gates to be oriented in the same direction.
    • Gates might even be required to lie on a periodic grid.
  • Cell height: Does a cell always occupy only one row or more (d)?
  • All transistors in the cell have same threshold voltage.

Algorithms for automatic cell synthesis will be based on such assumptions.

Core concepts

Netlist synthesis


Transistor folding

Transistor folding: A transistor can be split into N parallel transistors with an N-th of the original width.

A transistor of given width can have different implementations. The most basic is to put the whole gate into one piece. However, the transistor can also be folded into multiple smaller parallel transistors of shorter width which all together will have almost the same driving strength. This might be necessary if the transistor does not fit into the cell but it can also help finding alternative placement solutions.

Transistor folding can be done at the netlist level agnostic of the placement but also during placement to give the placement algorithm more degrees of freedom.


Given a set of transistors together with their connections a placement algorithms finds 'good' positions for the transistors. Placement might also include transistor folding.

During placement certain criteria need to be taken into account:

  • Cell width
  • Routability

Routability must somehow be estimated during placement. Indicators for good routability could be:

  • Perimeter of bounding box around all contacts of a net.
  • Gate matches: Transistor with shared gate nets should be aligned such that the gate can be implemented as a straight polysilicon line.

Pin placement

Pins are the interface of the cell to the circuit. Usually a pin is formed by a piece of metal on metal1 or metal2 that will be connected when routing the full circuit depending on the location of the pins and the surrounding shapes the pins can be accessed more or less easily by the router. Therefore, choosing good pin locations simplifies the work for the router.

A few rules of thumb can be applied to ensure easier inter-cell routing:

  • Place pins such that they occupy different routing tracks of the main routing direction. (Keeps pins accessible by using the main routing direction).
  • Prefer placing pins close to the borders of the cell such that there are no metal shapes blocking the path from the pin to the border.
  • Place input pins and output pins consistently on separate sites (left/right) of the cell. (Simplifies chaining of cells).

Some tools such as BonnCell let the user choose absolute or relative locations of the pins (see chapter 5.2.2 in [1]).


The placed transistors need to be connected in the physical layout such that the resulting circuit is equal to the original netlist. Routing is usually done polysilicon and lower metal layers.

Existing Work



ASTRAN is open source but uses a commercial ILP solver (Gurobi) in its last processing step.


BonnCell is a closed source cell generator with available documentation in the PhD thesis of Jan Schneider [1].


  • Placement
  • Routing (p.99 [1])
    • Combinatorial routing: Find vertex-disjoint Steiner trees.
    • Use MIP to resolve design rule violations in Steiner trees.
    • Post-processing: Apply some transformations to polygons to enhance conductivity and reduce electromigration.


LibreCell is a free & open-source tool for automated layout generation of CMOS standard-cells.


  • Placement
    • Graph theoretic: finding Eulerian trail graph coverings
    • SAT/SMT: Encode placement for SMT solver
  • Routing
    • Grid/Graph based: Modified PathFinder [1]
    • MIP (mixed integer programming) based

Algorithms Overview


  • Meta heuristic
    • simulated annealing
    • threshold-accept
  • Graph theoretic
    • Finding dual Eulerian trail coverings
  • Integer programming
  • SAT / SMT


  • Grid-based
    • Graph routing
    • SAT [2]
  • Grid-less

Post-Processing / DRC Cleaning

  • Using constraint solver


  1. 1.0 1.1 1.2 Transistor-Level Layout of Integrated Circuits, Jan Schneider, 2014,
  2. N. Ryzhenko and S. Burns, “Standard cell routing via boolean satisfiability,” in Proc. DAC’12, 2012, pp. 603-612