Moving toward VexiiRiscv

From F-Si wiki
Jump to navigation Jump to search
  • Speaker: Charles Papon
  • email:


  • Slides (to upload a file: go to Edit mode, then click on the fourth icon from the left "Images and media" and follow the instructions)


There is still very few free/open-source/multiple issue/in-order RISC-V CPU in the wild. In the same time, VexRiscv accumulated quite some technical debt and limitations. So it was time to fill those gaps !

VexiiRiscv aim at :

  • Providing a free/open-source CPU which can scale from simple micro controller, up to linux ready multi-core / multi-issue cluster (Cortex A53/A55 like)
  • Covering both 32 bits and 64 bits RISC-V + IMAFDC + B
  • Being very modular and extendable
  • Being Debian capable

This talk should normaly run on the hardware itself (FPGA), minus maybe, some kernel panics.


General information