VACASK: a Verilog-A Circuit Analysis Kernel

From F-Si wiki
Jump to navigation Jump to search
  • Speaker(s): Árpád Bűrmen (University of Ljubljana, Faculty of Electrical Engineering)
  • email: arpad.buermen [at]


  • Slides (TODO)


The Verilog-A Circuit AnalysiS Kernel (VACASK) is as an advanced analog circuit simulator, utilizing the cutting-edge OpenVAF Verilog-A compiler to construct its device models. This integration provides access to the latest models from the Compact Model Coalition (CMC). Crafted with a focus on accuracy, simplicity, flexibility, and maintainability, VACASK is implemented in C++ with a commitment to code clarity. The simulator relies on just two core dependencies: the KLU sparse matrix library and the standard C++ library.

VACASK boasts a versatile design, capable of parsing netlists with a syntax reminiscent of Spectre, or serving as a library seamlessly integrated with third-party software. Its capacity to analyze multiple circuit topologies in a single run makes it an ideal tool for circuit sizing and topology optimizations.

Equipped with an array of standard SPICE analyses including operating point, small-signal DC/AC response and transfer function, time-domain, and noise analyses, VACASK offers comprehensive insights into circuit behavior. Further enhancing its utility, the simulator supports parameter sweeps of any depth across analyses, while also providing common homotopy algorithms for addressing challenging circuit configurations.

We provide a comparative analysis with other free circuit simulators, discuss the developmental hurdles overcome during VACASK's evolution, and outline a roadmap for forthcoming feature implementations.


General information


  • Support legacy SPICE3 models (looking for funding)
  • Implement binning
  • Translate Skywater-PDK
  • Implement damped pseudo-transient operating point analysis
  • Improve handling of limiting functions
  • Implement harmonic balance analysis
  • Parallelization