Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana
- Speaker(s): Thomas Benz
- email: tbenz@iis.ee.ethz.ch
- other information: PhD student at IIS, ETH Zurich - Member of the PULP group
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Abstract
Recent advancements in FOSS EDA tools and the trend towards opening PDKs have enabled fully free and open-source ASIC design. However, open tools still lack feature completeness compared to their commercial counterparts, particularly in their support for SystemVerilog. Despite the emergence of alternative HDL languages and HLS approaches, many commercial and open-source IPs are still written in SystemVerilog.
This talk discusses our experience synthesizing Iguana, the first end-to-end FOS Linux-capable ASIC. We encounter challenges with SystemVerilog support of our IPs in various open tools as proper processing of many language constructs requires full elaboration. To bridge essential gaps in open frontend flows, we develop SVase, our own SystemVerilog pre-elaborator and simplifier based on the best-in-class Slang library. We present the technical details of SVase and its place in the synthesis flow of Iguana. Furthermore, we discuss the quality of results obtained from synthesizing Iguana with Yosys. Particularly two reasons for a significant increase in the area and the critical path in some modules of the design.
Software
General information
- Repository:
- https://github.com/pulp-platform/iguana (we are in the process of releasing Iguana, which will be online during the next few weeks)
- https://github.com/pulp-platform/svase
Roadmap
- The project seeks help on:
- Improving SVase to simplify more constructs no longer requiring SV2V
- Improving the generic mapping and part select implementation of Yosys
- Using slang directly to read in SystemVerilog into Yosys