Composing an out-of-order CPU using software technics
- Speaker(s): Charles Papon
- email: email@example.com
- other information: Dolu1990 (Github)
This talk will introduce the paradigm in which NaxRiscv (a recently developed out of order / super-scalar / RISC-V core) was developped.
The project is using Scala (A general purpose programming language), SpinalHDL (A Scala hardware generation library) and many software techniques to elaborate a synthetisable CPU. The combination of those 3 elements makes the core very portable and extendable while not degrading the performances nor the area usage of the core.
During the talk we will very briefly introduce the core and then dive in the concepts and the code.
- Repository: https://github.com/SpinalHDL/NaxRiscv
- Main documentation website: https://spinalhdl.github.io/NaxRiscv-Rtd/main/NaxRiscv/introduction/index.html
- Debian support (rv64imafdc)
- Multicore with memory coherency support