Caravel Panamax: The Next Generation

From F-Si wiki
Jump to navigation Jump to search
  • Speaker: Tim Edwards
  • Email:
  • Other information: Efabless website



The Efabless "Caravel" harness chip has been the foundation of enablement for open source silicon, introduced in 2020 for the first Google-sponsored Open MPW with SkyWater foundry. The Caravel chip aims to simplify full-chip design by providing a padframe, processor, and other infrastructure around an empty area to be filled with a custom layout. This original architecture carried through nine Open MPW shuttle runs and the Efabless chipIgnite program, and was adapted for the two GlobalFoundries Open MPWs. After four years, it's time for an upgrade! "Caravel Panamax" is intended to support machine learning edge applications, with ultra-low-power modes of operation, more SRAM, a Hazard-3 RISC-V processor, and an array of on-chip sensors and data converters with full access to the user project area. With 128 pins and numerous specialty I/Os, Panamax opens the door to a vast array of potential user designs. With a test version taped out in June, Caravel Panamax should be available for chipIgnite shuttle runs by early 2025.


General information