Pages without language links

Jump to navigation Jump to search

The following pages do not link to other language versions.

Showing below up to 126 results in range #21 to #146.

View (previous 250 | next 250) (20 | 50 | 100 | 250 | 500)

  1. Converting 45nm transistor netlists to open standards
  2. Coriolis (installation)
  3. Coriolis (tutorials)
  4. Coriolis a RTL to GDSII FOSS Design Flow
  5. Degate: The stakes and challenges of silicon reverse engineering
  6. Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology
  7. Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes
  8. Digital placement algorithms in Coriolis
  9. E-Waste Reverse Engineering Toolkit (RET)
  10. Environmental impacts of electronics and the role of open source hardware
  11. Exploring open hardware solutions for ensuring the security of RISC-V processors
  12. F-Si Donations
  13. F-Si Statute
  14. F8
  15. FOS standard cell generator from scratch
  16. FSiC2019
  17. FSiC2019 reimbursement
  18. FSiC2019 venue
  19. FSiC2020
  20. FSiC2021
  21. FSiC2022
  22. FSiC2022 venue
  23. FSiC2023
  24. FSiC2023 venue
  25. FSiC2024
  26. FSiC2024 venue
  27. Free Silicon Foundation
  28. From CMOS transistors to filters - A library of analog schematics with automated sizing
  29. From Theory to Tape-Out: Chip Design Education with Edu4Chip
  30. From filters to CMOS transistors - A library of analog schematics with automated sizing
  31. From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD
  32. GAUT
  33. GAUT - A Free and Open-Source High-Level Synthesis tool
  34. GHDL and the economy of EDA FOSS
  35. Gdsfactory
  36. GnuCap: Progress and Opportunities
  37. Gnu Circuit Analysis Package (GnuCap)
  38. Go2async: A high-level synthesis tool for asynchronous circuits
  39. Guidelines for speakers
  40. Hands-on with KLayout: Design rule checks and layout to netlist tools
  41. High level Simulation
  42. High level system modelling, hands-on computer session
  43. Horizon 2021 Coordination and Support Action (CSA) proposal
  44. How many designs can you fit on a single die
  45. How to foster GreenIT through open hardware?
  46. Inclusive Modeling with SysMD
  47. Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana
  48. Introduction to the GoIT project
  49. KLayout's deep verification base project
  50. KLayout XSection tool - Deep insights or nonsense in colors?
  51. KQCircuits – open-source EDA software for designing chips with super conducting qubits
  52. KiCad
  53. LIP6 Welcome
  54. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks
  55. Learning hardware design in the video game Minecraft
  56. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon
  57. LibrEDA
  58. LibrEDA - digital place-and-route framework from scratch
  59. LibreCell
  60. Libre Silicon Compiler
  61. LiteX: an open-source SoC builder and library based on Migen Python DSL
  62. Main Page
  63. Main Page/Software
  64. Matthias:UnsortedThroughsOnFOSSForEDA
  65. Merging Gnucap and Qucs -- The Why and How
  66. Mixed-signal system modelling and simulation
  67. Mixing software abstractions for high-level FPGA programming
  68. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design
  69. Naja: an open source framework for EDA post synthesis flow development
  70. Naja: project updates and netlist splitting tool
  71. Need for a free alternative to OpenAccess (by Matthias)
  72. Ngspice - an open source mixed signal circuit simulator
  73. Open-source electronic design automation for agile network defense at OVHcloud
  74. OpenEPDA: photonic PDKs with open standards
  75. OpenRAM: An Open-Source Memory Compiler
  76. OpenROAD
  77. OpenSource PDK - A key enabler to unlock the potential of an open source design flow
  78. Open (and Closed) Source Analog Design with Hdl21 & VLSIR
  79. Open Source Parasitic Extraction
  80. Open Source for Sustainable and Long lasting Phones
  81. Open Source in Healthcare, an hardware approach: the echOpen project case
  82. Open source Design Flow status and roadmap for IHP BiCMOS technology
  83. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries
  84. Physical security for cryptographic implementations with open hardware
  85. Placement algorithms for standard cells in Coriolis
  86. Porting software to hardware using XLS and open source PDKs
  87. Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites
  88. Proof-of-concept for scalable analog blocks using the PDKMaster framework
  89. Recent Developments from YosysHQ
  90. Recommendations and roadmap for the development of open-source silicon in the EU
  91. Recommendations for the EC on how to reduce the environmental impact of the ICT sector
  92. Revolutionize your chip design with GDSFactory and Open Source PDKs
  93. Software-Defined Hardware: Digital Design in the 21st Century with Chisel
  94. Standard-cell characterization
  95. Standard-cell recognition
  96. Standard-cell synthesis
  97. Standard Cell Library report
  98. Statute of the Free Silicon Foundation (I) ETS
  99. Synthesis with ghdl
  100. SystemC AMS and upcoming free frameworks for the free design
  101. Teaching Chip Design with Open-Source Tools
  102. TestPageX
  103. The ACT EDA flow for asynchronous logic
  104. The Alliance/Coriolis design flow
  105. The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies
  106. The Raven chip: First-time silicon success with qflow and efabless
  107. The development of the NSXLIB standard cell scalable library
  108. The importance of EU Academia in developing the chips of the future
  109. The open-source and low-cost echo-stethoscope project
  110. The road to fully open hardware mobile computing
  111. TinyTapeout - what happened and next steps
  112. Toward a collaborative environment for Open Hardware Design
  113. Toward multi-language open-source HDL simulation
  114. Towards digital sovereignty by open source (hardware)
  115. Tutorial and FAQ on physical verification, DRC+LVS
  116. VACASK: a Verilog-A Circuit Analysis Kernel
  117. Verilog-AMS in Gnucap
  118. Verilog-AMS in Gnucap (2024)
  119. Verilog-A Circuit Analysis Kernel (VACASK)
  120. Welcome from LIP6
  121. Welcome from the Free Silicon Foundation 2023
  122. White paper for the EC, January 2020
  123. Whom do you trust?: Validating process parameters for open-source tools
  124. Wiki/openic
  125. Wishbone: a free SoC bus family
  126. XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design

View (previous 250 | next 250) (20 | 50 | 100 | 250 | 500)

Retrieved from "https://wiki.f-si.org/index.php?title=Special:WithoutInterwiki"