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Showing below up to 80 results in range #71 to #150.
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- F8 (22:47, 1 August 2022)
- OpenEPDA: photonic PDKs with open standards (22:56, 1 August 2022)
- Merging Gnucap and Qucs -- The Why and How (22:59, 1 August 2022)
- Whom do you trust?: Validating process parameters for open-source tools (23:00, 1 August 2022)
- LibrEDA - digital place-and-route framework from scratch (23:00, 1 August 2022)
- Digital placement algorithms in Coriolis (23:01, 1 August 2022)
- Naja: an open source framework for EDA post synthesis flow development (23:02, 1 August 2022)
- Tutorial and FAQ on physical verification, DRC+LVS (23:05, 1 August 2022)
- 65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview (11:16, 23 August 2022)
- Wiki/openic (04:02, 4 September 2022)
- LibreCell (00:34, 16 December 2022)
- Standard-cell synthesis (15:48, 2 February 2023)
- FSiC2023 venue (15:12, 2 July 2023)
- TestPageX (14:14, 8 July 2023)
- Naja: project updates and netlist splitting tool (22:32, 9 July 2023)
- E-Waste Reverse Engineering Toolkit (RET) (00:05, 11 July 2023)
- Software-Defined Hardware: Digital Design in the 21st Century with Chisel (22:13, 28 July 2023)
- A progressive introduction to memory bus interconnect API in Software-Defined Hardware (22:14, 28 July 2023)
- Mixing software abstractions for high-level FPGA programming (22:14, 28 July 2023)
- Toward multi-language open-source HDL simulation (22:15, 28 July 2023)
- Recent Developments from YosysHQ (22:15, 28 July 2023)
- Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry? (22:16, 28 July 2023)
- Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana (22:16, 28 July 2023)
- Proof-of-concept for scalable analog blocks using the PDKMaster framework (22:16, 28 July 2023)
- Open source Design Flow status and roadmap for IHP BiCMOS technology (22:17, 28 July 2023)
- TinyTapeout - what happened and next steps (22:18, 28 July 2023)
- Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites (22:18, 28 July 2023)
- Analyzing open-source chip design ecosystem from an environmental sustainability perspective (22:19, 28 July 2023)
- Open Source for Sustainable and Long lasting Phones (22:19, 28 July 2023)
- Open-source electronic design automation for agile network defense at OVHcloud (22:20, 28 July 2023)
- Physical security for cryptographic implementations with open hardware (22:20, 28 July 2023)
- Black-tie Python: Formal verification with Amaranth (22:21, 28 July 2023)
- Exploring open hardware solutions for ensuring the security of RISC-V processors (22:21, 28 July 2023)
- A Yosys plugin for logic locking (22:22, 28 July 2023)
- All you ever wanted to know about side-channel attacks and protections (and a forthcoming book) (22:22, 28 July 2023)
- Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology (22:22, 28 July 2023)
- Verilog-AMS in Gnucap (22:23, 28 July 2023)
- How to foster GreenIT through open hardware? (22:24, 28 July 2023)
- The importance of EU Academia in developing the chips of the future (22:25, 28 July 2023)
- Open (and Closed) Source Analog Design with Hdl21 & VLSIR (22:26, 28 July 2023)
- An overview of libre silicon and OSHW related efforts within NGI and NLnet (22:27, 28 July 2023)
- KQCircuits – open-source EDA software for designing chips with super conducting qubits (22:28, 28 July 2023)
- Coriolis a RTL to GDSII FOSS Design Flow (22:28, 28 July 2023)
- Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks (22:29, 28 July 2023)
- Teaching Chip Design with Open-Source Tools (22:29, 28 July 2023)
- Learning hardware design in the video game Minecraft (22:29, 28 July 2023)
- Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks (22:29, 28 July 2023)
- OpenROAD (12:09, 11 August 2023)
- The road to fully open hardware mobile computing (15:08, 24 August 2023)
- Introduction to the GoIT project (15:11, 24 August 2023)
- Welcome from LIP6 (16:23, 24 August 2023)
- Welcome from the Free Silicon Foundation 2023 (16:24, 24 August 2023)
- Recommendations for the EC on how to reduce the environmental impact of the ICT sector (22:10, 30 September 2023)
- FSiC2023 (17:08, 1 October 2023)
- FSiC2022 (17:09, 1 October 2023)
- FSiC2019 (17:09, 1 October 2023)
- Environmental impacts of electronics and the role of open source hardware (16:34, 20 October 2023)
- Recommendations and roadmap for the development of open-source silicon in the EU (19:13, 3 November 2023)
- Main Page (17:24, 25 January 2024)
- Free Silicon Foundation (14:57, 31 January 2024)
- Gdsfactory (11:21, 6 March 2024)
- Statute of the Free Silicon Foundation (I) ETS (17:47, 28 March 2024)
- Guidelines for speakers (19:17, 22 April 2024)
- Revolutionize your chip design with GDSFactory and Open Source PDKs (20:49, 22 April 2024)
- Verilog-A Circuit Analysis Kernel (VACASK) (08:54, 23 April 2024)
- The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies (09:04, 23 April 2024)
- Degate: The stakes and challenges of silicon reverse engineering (19:32, 23 April 2024)
- From Theory to Tape-Out: Chip Design Education with Edu4Chip (15:04, 24 April 2024)
- The ACT EDA flow for asynchronous logic (17:08, 24 April 2024)
- VACASK: a Verilog-A Circuit Analysis Kernel (15:35, 25 April 2024)
- Verilog-AMS in Gnucap (2024) (16:09, 25 April 2024)
- Caravel Panamax: The Next Generation (22:19, 30 April 2024)
- CACE: Defining an open-source analog and mixed-signal design flow (22:29, 30 April 2024)
- An opensource Wi-Fi chip, What, Why and How? (09:32, 2 May 2024)
- Moving toward VexiiRiscv (23:39, 2 May 2024)
- Generating DRC Runsets for IHP's OpenPDK - Lessons Learned (13:39, 3 May 2024)
- F-Si Statute (14:57, 8 May 2024)
- FSiC2024 venue (20:05, 8 May 2024)
- PyOpus - a Python library for design automation (11:46, 9 May 2024)
- FSiC2024 (16:59, 16 May 2024)