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Showing below up to 100 results in range #31 to #130.

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31. Merging Gnucap and Qucs -- The Why and How‏‎ (8 revisions)
32. Wiki/openic‏‎ (8 revisions)
33. KLayout XSection tool - Deep insights or nonsense in colors?‏‎ (8 revisions)
34. Need for a free alternative to OpenAccess (by Matthias)‏‎ (8 revisions)
35. The development of the NSXLIB standard cell scalable library‏‎ (8 revisions)
36. Environmental impacts of electronics and the role of open source hardware‏‎ (8 revisions)
37. Mixed-signal system modelling and simulation‏‎ (8 revisions)
38. Standard-cell synthesis‏‎ (8 revisions)
39. FSiC2023 venue‏‎ (8 revisions)
40. Coriolis (installation)‏‎ (7 revisions)
41. Gnu Circuit Analysis Package (GnuCap)‏‎ (7 revisions)
42. TinyTapeout - what happened and next steps‏‎ (7 revisions)
43. Challenge to Fabricate LSI without NDA with Open Method‏‎ (7 revisions)
44. FSiC2021‏‎ (7 revisions)
45. Verilog-A Circuit Analysis Kernel (VACASK)‏‎ (7 revisions)
46. Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology‏‎ (7 revisions)
47. KQCircuits – open-source EDA software for designing chips with super conducting qubits‏‎ (7 revisions)
48. Toward a collaborative environment for Open Hardware Design‏‎ (7 revisions)
49. F8‏‎ (6 revisions)
50. The importance of EU Academia in developing the chips of the future‏‎ (6 revisions)
51. ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals‏‎ (6 revisions)
52. GAUT - A Free and Open-Source High-Level Synthesis tool‏‎ (6 revisions)
53. Black-tie Python: Formal verification with Amaranth‏‎ (6 revisions)
54. LibrEDA - digital place-and-route framework from scratch‏‎ (6 revisions)
55. PyOpus - a Python library for design automation‏‎ (6 revisions)
56. Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks‏‎ (6 revisions)
57. The Alliance/Coriolis design flow‏‎ (6 revisions)
58. GHDL and the economy of EDA FOSS‏‎ (6 revisions)
59. Learning hardware design in the video game Minecraft‏‎ (5 revisions)
60. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries‏‎ (5 revisions)
61. A Yosys plugin for logic locking‏‎ (5 revisions)
62. White paper for the EC, January 2020‏‎ (5 revisions)
63. CERN OHL v2 draft‏‎ (5 revisions)
64. Open source Design Flow status and roadmap for IHP BiCMOS technology‏‎ (5 revisions)
65. The Raven chip: First-time silicon success with qflow and efabless‏‎ (5 revisions)
66. Digital placement algorithms in Coriolis‏‎ (5 revisions)
67. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks‏‎ (5 revisions)
68. Towards digital sovereignty by open source (hardware)‏‎ (5 revisions)
69. Whom do you trust?: Validating process parameters for open-source tools‏‎ (5 revisions)
70. F-Si Donations‏‎ (5 revisions)
71. Standard-cell recognition‏‎ (5 revisions)
72. OpenROAD‏‎ (5 revisions)
73. FSiC2024 venue‏‎ (5 revisions)
74. From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD‏‎ (5 revisions)
75. Welcome from LIP6‏‎ (5 revisions)
76. Exploring open hardware solutions for ensuring the security of RISC-V processors‏‎ (5 revisions)
77. Tutorial and FAQ on physical verification, DRC+LVS‏‎ (5 revisions)
78. Proof-of-concept for scalable analog blocks using the PDKMaster framework‏‎ (5 revisions)
79. Welcome from the Free Silicon Foundation 2023‏‎ (4 revisions)
80. Physical security for cryptographic implementations with open hardware‏‎ (4 revisions)
81. Toward multi-language open-source HDL simulation‏‎ (4 revisions)
82. Verilog-AMS in Gnucap‏‎ (4 revisions)
83. Go2async: A high-level synthesis tool for asynchronous circuits‏‎ (4 revisions)
84. Placement algorithms for standard cells in Coriolis‏‎ (4 revisions)
85. Recent Developments from YosysHQ‏‎ (4 revisions)
86. Recommendations and roadmap for the development of open-source silicon in the EU‏‎ (4 revisions)
87. Moving toward VexiiRiscv‏‎ (4 revisions)
88. All you ever wanted to know about side-channel attacks and protections (and a forthcoming book)‏‎ (4 revisions)
89. F-Si Statute‏‎ (4 revisions)
90. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon‏‎ (4 revisions)
91. Main Page/Software‏‎ (4 revisions)
92. Open Source for Sustainable and Long lasting Phones‏‎ (4 revisions)
93. High level Simulation‏‎ (4 revisions)
94. Open (and Closed) Source Analog Design with Hdl21 & VLSIR‏‎ (4 revisions)
95. ASICone. Goals, timeline, participants and tools‏‎ (3 revisions)
96. Composing an out-of-order CPU using software technics‏‎ (3 revisions)
97. Naja: an open source framework for EDA post synthesis flow development‏‎ (3 revisions)
98. GnuCap: Progress and Opportunities‏‎ (3 revisions)
99. XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design‏‎ (3 revisions)
100. An overview of libre silicon and OSHW related efforts within NGI and NLnet‏‎ (3 revisions)
101. OpenSource PDK - A key enabler to unlock the potential of an open source design flow‏‎ (3 revisions)
102. Free Silicon Foundation‏‎ (3 revisions)
103. Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites‏‎ (3 revisions)
104. The road to fully open hardware mobile computing‏‎ (3 revisions)
105. Porting software to hardware using XLS and open source PDKs‏‎ (3 revisions)
106. How to foster GreenIT through open hardware?‏‎ (3 revisions)
107. CMOS functional abstraction‏‎ (3 revisions)
108. Open-source electronic design automation for agile network defense at OVHcloud‏‎ (3 revisions)
109. LibrEDA‏‎ (3 revisions)
110. How many designs can you fit on a single die‏‎ (3 revisions)
111. Recommendations for the EC on how to reduce the environmental impact of the ICT sector‏‎ (3 revisions)
112. OpenEPDA: photonic PDKs with open standards‏‎ (3 revisions)
113. Ngspice - an open source mixed signal circuit simulator‏‎ (3 revisions)
114. Generating DRC Runsets for IHP's OpenPDK - Lessons Learned‏‎ (2 revisions)
115. Naja: project updates and netlist splitting tool‏‎ (2 revisions)
116. Open Source in Healthcare, an hardware approach: the echOpen project case‏‎ (2 revisions)
117. Converting 45nm transistor netlists to open standards‏‎ (2 revisions)
118. Degate: The stakes and challenges of silicon reverse engineering‏‎ (2 revisions)
119. Analyzing open-source chip design ecosystem from an environmental sustainability perspective‏‎ (2 revisions)
120. Verilog-AMS in Gnucap (2024)‏‎ (2 revisions)
121. FSiC2019 reimbursement‏‎ (2 revisions)
122. Synthesis with ghdl‏‎ (2 revisions)
123. Standard Cell Library report‏‎ (2 revisions)
124. A progressive introduction to memory bus interconnect API in Software-Defined Hardware‏‎ (2 revisions)
125. Gdsfactory‏‎ (2 revisions)
126. Coriolis a RTL to GDSII FOSS Design Flow‏‎ (2 revisions)
127. From CMOS transistors to filters - A library of analog schematics with automated sizing‏‎ (2 revisions)
128. TestPageX‏‎ (2 revisions)
129. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design‏‎ (2 revisions)
130. Wishbone: a free SoC bus family‏‎ (2 revisions)

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