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Showing below up to 100 results in range #41 to #140.

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  1. FSiC2021
  2. FSiC2022
  3. FSiC2022 venue
  4. FSiC2023
  5. FSiC2023 venue
  6. FSiC2024
  7. FSiC2024 venue
  8. Free Silicon Foundation
  9. From CMOS transistors to filters - A library of analog schematics with automated sizing
  10. From Theory to Tape-Out: Chip Design Education with Edu4Chip
  11. From filters to CMOS transistors - A library of analog schematics with automated sizing
  12. From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD
  13. GAUT
  14. GAUT - A Free and Open-Source High-Level Synthesis tool
  15. GHDL and the economy of EDA FOSS
  16. Gdsfactory
  17. Generating DRC Runsets for IHP's OpenPDK - Lessons Learned
  18. GnuCap: Progress and Opportunities
  19. Gnu Circuit Analysis Package (GnuCap)
  20. Go2async: A high-level synthesis tool for asynchronous circuits
  21. Guidelines for speakers
  22. Hands-on with KLayout: Design rule checks and layout to netlist tools
  23. High level Simulation
  24. High level system modelling, hands-on computer session
  25. Horizon 2021 Coordination and Support Action (CSA) proposal
  26. How many designs can you fit on a single die
  27. How to foster GreenIT through open hardware?
  28. Inclusive Modeling with SysMD
  29. Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana
  30. Introduction to the GoIT project
  31. KLayout's deep verification base project
  32. KLayout XSection tool - Deep insights or nonsense in colors?
  33. KQCircuits – open-source EDA software for designing chips with super conducting qubits
  34. KiCad
  35. LIP6 Welcome
  36. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks
  37. Learning hardware design in the video game Minecraft
  38. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon
  39. LibrEDA
  40. LibrEDA - digital place-and-route framework from scratch
  41. LibreCell
  42. Libre Silicon Compiler
  43. LiteX: an open-source SoC builder and library based on Migen Python DSL
  44. Main Page
  45. Main Page/Software
  46. Matthias:UnsortedThroughsOnFOSSForEDA
  47. Merging Gnucap and Qucs -- The Why and How
  48. Mixed-signal system modelling and simulation
  49. Mixing software abstractions for high-level FPGA programming
  50. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design
  51. Moving toward VexiiRiscv
  52. Naja: an open source framework for EDA post synthesis flow development
  53. Naja: project updates and netlist splitting tool
  54. Need for a free alternative to OpenAccess (by Matthias)
  55. Ngspice - an open source mixed signal circuit simulator
  56. Open-source electronic design automation for agile network defense at OVHcloud
  57. OpenEPDA: photonic PDKs with open standards
  58. OpenRAM: An Open-Source Memory Compiler
  59. OpenROAD
  60. OpenSource PDK - A key enabler to unlock the potential of an open source design flow
  61. Open (and Closed) Source Analog Design with Hdl21 & VLSIR
  62. Open Source Parasitic Extraction
  63. Open Source for Sustainable and Long lasting Phones
  64. Open Source in Healthcare, an hardware approach: the echOpen project case
  65. Open source Design Flow status and roadmap for IHP BiCMOS technology
  66. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries
  67. Physical security for cryptographic implementations with open hardware
  68. Placement algorithms for standard cells in Coriolis
  69. Porting software to hardware using XLS and open source PDKs
  70. Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites
  71. Proof-of-concept for scalable analog blocks using the PDKMaster framework
  72. PyOpus - a Python library for design automation
  73. Recent Developments from YosysHQ
  74. Recommendations and roadmap for the development of open-source silicon in the EU
  75. Recommendations for the EC on how to reduce the environmental impact of the ICT sector
  76. Revolutionize your chip design with GDSFactory and Open Source PDKs
  77. Software-Defined Hardware: Digital Design in the 21st Century with Chisel
  78. Standard-cell characterization
  79. Standard-cell recognition
  80. Standard-cell synthesis
  81. Standard Cell Library report
  82. Statute of the Free Silicon Foundation (I) ETS
  83. Synthesis with ghdl
  84. SystemC AMS and upcoming free frameworks for the free design
  85. Teaching Chip Design with Open-Source Tools
  86. TestPageX
  87. The ACT EDA flow for asynchronous logic
  88. The Alliance/Coriolis design flow
  89. The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies
  90. The Raven chip: First-time silicon success with qflow and efabless
  91. The development of the NSXLIB standard cell scalable library
  92. The importance of EU Academia in developing the chips of the future
  93. The open-source and low-cost echo-stethoscope project
  94. The road to fully open hardware mobile computing
  95. TinyTapeout - what happened and next steps
  96. Toward a collaborative environment for Open Hardware Design
  97. Toward multi-language open-source HDL simulation
  98. Towards digital sovereignty by open source (hardware)
  99. Tutorial and FAQ on physical verification, DRC+LVS
  100. VACASK: a Verilog-A Circuit Analysis Kernel

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