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Showing below up to 100 results in range #21 to #120.

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  1. Composing an out-of-order CPU using software technics
  2. Converting 45nm transistor netlists to open standards
  3. Coriolis (installation)
  4. Coriolis (tutorials)
  5. Coriolis a RTL to GDSII FOSS Design Flow
  6. Degate: The stakes and challenges of silicon reverse engineering
  7. Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology
  8. Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes
  9. Digital placement algorithms in Coriolis
  10. E-Waste Reverse Engineering Toolkit (RET)
  11. Environmental impacts of electronics and the role of open source hardware
  12. Exploring open hardware solutions for ensuring the security of RISC-V processors
  13. F-Si Donations
  14. F-Si Statute
  15. F8
  16. FOS standard cell generator from scratch
  17. FSiC2019
  18. FSiC2019 reimbursement
  19. FSiC2019 venue
  20. FSiC2020
  21. FSiC2021
  22. FSiC2022
  23. FSiC2022 venue
  24. FSiC2023
  25. FSiC2023 venue
  26. FSiC2024
  27. FSiC2024 venue
  28. Free Silicon Foundation
  29. From CMOS transistors to filters - A library of analog schematics with automated sizing
  30. From Theory to Tape-Out: Chip Design Education with Edu4Chip
  31. From filters to CMOS transistors - A library of analog schematics with automated sizing
  32. From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD
  33. GAUT
  34. GAUT - A Free and Open-Source High-Level Synthesis tool
  35. GHDL and the economy of EDA FOSS
  36. Gdsfactory
  37. GnuCap: Progress and Opportunities
  38. Gnu Circuit Analysis Package (GnuCap)
  39. Go2async: A high-level synthesis tool for asynchronous circuits
  40. Guidelines for speakers
  41. Hands-on with KLayout: Design rule checks and layout to netlist tools
  42. High level Simulation
  43. High level system modelling, hands-on computer session
  44. Horizon 2021 Coordination and Support Action (CSA) proposal
  45. How many designs can you fit on a single die
  46. How to foster GreenIT through open hardware?
  47. Inclusive Modeling with SysMD
  48. Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana
  49. Introduction to the GoIT project
  50. KLayout's deep verification base project
  51. KLayout XSection tool - Deep insights or nonsense in colors?
  52. KQCircuits – open-source EDA software for designing chips with super conducting qubits
  53. KiCad
  54. LIP6 Welcome
  55. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks
  56. Learning hardware design in the video game Minecraft
  57. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon
  58. LibrEDA
  59. LibrEDA - digital place-and-route framework from scratch
  60. LibreCell
  61. Libre Silicon Compiler
  62. LiteX: an open-source SoC builder and library based on Migen Python DSL
  63. Main Page
  64. Main Page/Software
  65. Matthias:UnsortedThroughsOnFOSSForEDA
  66. Merging Gnucap and Qucs -- The Why and How
  67. Mixed-signal system modelling and simulation
  68. Mixing software abstractions for high-level FPGA programming
  69. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design
  70. Naja: an open source framework for EDA post synthesis flow development
  71. Naja: project updates and netlist splitting tool
  72. Need for a free alternative to OpenAccess (by Matthias)
  73. Ngspice - an open source mixed signal circuit simulator
  74. Open-source electronic design automation for agile network defense at OVHcloud
  75. OpenEPDA: photonic PDKs with open standards
  76. OpenRAM: An Open-Source Memory Compiler
  77. OpenROAD
  78. OpenSource PDK - A key enabler to unlock the potential of an open source design flow
  79. Open (and Closed) Source Analog Design with Hdl21 & VLSIR
  80. Open Source Parasitic Extraction
  81. Open Source for Sustainable and Long lasting Phones
  82. Open Source in Healthcare, an hardware approach: the echOpen project case
  83. Open source Design Flow status and roadmap for IHP BiCMOS technology
  84. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries
  85. Physical security for cryptographic implementations with open hardware
  86. Placement algorithms for standard cells in Coriolis
  87. Porting software to hardware using XLS and open source PDKs
  88. Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites
  89. Proof-of-concept for scalable analog blocks using the PDKMaster framework
  90. Recent Developments from YosysHQ
  91. Recommendations and roadmap for the development of open-source silicon in the EU
  92. Recommendations for the EC on how to reduce the environmental impact of the ICT sector
  93. Revolutionize your chip design with GDSFactory and Open Source PDKs
  94. Software-Defined Hardware: Digital Design in the 21st Century with Chisel
  95. Standard-cell characterization
  96. Standard-cell recognition
  97. Standard-cell synthesis
  98. Standard Cell Library report
  99. Statute of the Free Silicon Foundation (I) ETS
  100. Synthesis with ghdl

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