Pages without language links

Jump to navigation Jump to search

The following pages do not link to other language versions.

Showing below up to 100 results in range #1 to #100.

View (previous 100 | next 100) (20 | 50 | 100 | 250 | 500)

  1. 65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview
  2. ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals
  3. ASICone. Goals, timeline, participants and tools
  4. A Yosys plugin for logic locking
  5. A progressive introduction to memory bus interconnect API in Software-Defined Hardware
  6. Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks
  7. All you ever wanted to know about side-channel attacks and protections (and a forthcoming book)
  8. An overview of libre silicon and OSHW related efforts within NGI and NLnet
  9. Analyzing open-source chip design ecosystem from an environmental sustainability perspective
  10. Black-tie Python: Formal verification with Amaranth
  11. CERN OHL v2 draft
  12. CERN Open Hardware License (OHL)
  13. CIAN Team Welcome
  14. CMOS functional abstraction
  15. CMP add on services - Towards Foundry PDKs on Free CAD Tools
  16. Challenge to Fabricate LSI without NDA with Open Method
  17. Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry?
  18. Composing an out-of-order CPU using software technics
  19. Converting 45nm transistor netlists to open standards
  20. Coriolis (installation)
  21. Coriolis (tutorials)
  22. Coriolis a RTL to GDSII FOSS Design Flow
  23. Degate: The stakes and challenges of silicon reverse engineering
  24. Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology
  25. Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes
  26. Digital placement algorithms in Coriolis
  27. E-Waste Reverse Engineering Toolkit (RET)
  28. Environmental impacts of electronics and the role of open source hardware
  29. Exploring open hardware solutions for ensuring the security of RISC-V processors
  30. F-Si Donations
  31. F-Si Statute
  32. F8
  33. FOS standard cell generator from scratch
  34. FSiC2019
  35. FSiC2019 reimbursement
  36. FSiC2019 venue
  37. FSiC2020
  38. FSiC2021
  39. FSiC2022
  40. FSiC2022 venue
  41. FSiC2023
  42. FSiC2023 venue
  43. FSiC2024
  44. FSiC2024 venue
  45. Free Silicon Foundation
  46. From CMOS transistors to filters - A library of analog schematics with automated sizing
  47. From Theory to Tape-Out: Chip Design Education with Edu4Chip
  48. From filters to CMOS transistors - A library of analog schematics with automated sizing
  49. From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD
  50. GAUT
  51. GAUT - A Free and Open-Source High-Level Synthesis tool
  52. GHDL and the economy of EDA FOSS
  53. Gdsfactory
  54. GnuCap: Progress and Opportunities
  55. Gnu Circuit Analysis Package (GnuCap)
  56. Go2async: A high-level synthesis tool for asynchronous circuits
  57. Guidelines for speakers
  58. Hands-on with KLayout: Design rule checks and layout to netlist tools
  59. High level Simulation
  60. High level system modelling, hands-on computer session
  61. Horizon 2021 Coordination and Support Action (CSA) proposal
  62. How many designs can you fit on a single die
  63. How to foster GreenIT through open hardware?
  64. Inclusive Modeling with SysMD
  65. Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana
  66. Introduction to the GoIT project
  67. KLayout's deep verification base project
  68. KLayout XSection tool - Deep insights or nonsense in colors?
  69. KQCircuits – open-source EDA software for designing chips with super conducting qubits
  70. KiCad
  71. LIP6 Welcome
  72. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks
  73. Learning hardware design in the video game Minecraft
  74. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon
  75. LibrEDA
  76. LibrEDA - digital place-and-route framework from scratch
  77. LibreCell
  78. Libre Silicon Compiler
  79. LiteX: an open-source SoC builder and library based on Migen Python DSL
  80. Main Page
  81. Main Page/Software
  82. Matthias:UnsortedThroughsOnFOSSForEDA
  83. Merging Gnucap and Qucs -- The Why and How
  84. Mixed-signal system modelling and simulation
  85. Mixing software abstractions for high-level FPGA programming
  86. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design
  87. Naja: an open source framework for EDA post synthesis flow development
  88. Naja: project updates and netlist splitting tool
  89. Need for a free alternative to OpenAccess (by Matthias)
  90. Ngspice - an open source mixed signal circuit simulator
  91. Open-source electronic design automation for agile network defense at OVHcloud
  92. OpenEPDA: photonic PDKs with open standards
  93. OpenRAM: An Open-Source Memory Compiler
  94. OpenROAD
  95. OpenSource PDK - A key enabler to unlock the potential of an open source design flow
  96. Open (and Closed) Source Analog Design with Hdl21 & VLSIR
  97. Open Source Parasitic Extraction
  98. Open Source for Sustainable and Long lasting Phones
  99. Open Source in Healthcare, an hardware approach: the echOpen project case
  100. Open source Design Flow status and roadmap for IHP BiCMOS technology

View (previous 100 | next 100) (20 | 50 | 100 | 250 | 500)

Retrieved from "https://wiki.f-si.org/index.php?title=Special:WithoutInterwiki"