Long pages

Showing below up to 50 results in range #71 to #120.

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71. (hist) ‎KLayout's deep verification base project ‎[1,423 bytes]
72. (hist) ‎Exploring open hardware solutions for ensuring the security of RISC-V processors ‎[1,405 bytes]
73. (hist) ‎Open Source for Sustainable and Long lasting Phones ‎[1,401 bytes]
74. (hist) ‎Caravel Panamax: The Next Generation ‎[1,400 bytes]
75. (hist) ‎From CMOS transistors to filters - A library of analog schematics with automated sizing ‎[1,381 bytes]
76. (hist) ‎Revolutionize your chip design with GDSFactory and Open Source PDKs ‎[1,371 bytes]
77. (hist) ‎All you ever wanted to know about side-channel attacks and protections (and a forthcoming book) ‎[1,365 bytes]
78. (hist) ‎Whom do you trust?: Validating process parameters for open-source tools ‎[1,363 bytes]
79. (hist) ‎Porting software to hardware using XLS and open source PDKs ‎[1,321 bytes]
80. (hist) ‎Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites ‎[1,271 bytes]
81. (hist) ‎Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks ‎[1,225 bytes]
82. (hist) ‎Verilog-AMS in Gnucap ‎[1,222 bytes]
83. (hist) ‎ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals ‎[1,221 bytes]
84. (hist) ‎XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design ‎[1,205 bytes]
85. (hist) ‎F8 ‎[1,193 bytes]
86. (hist) ‎Composing an out-of-order CPU using software technics ‎[1,190 bytes]
87. (hist) ‎GHDL and the economy of EDA FOSS ‎[1,185 bytes]
88. (hist) ‎Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks ‎[1,183 bytes]
89. (hist) ‎From Theory to Tape-Out: Chip Design Education with Edu4Chip ‎[1,172 bytes]
90. (hist) ‎An opensource Wi-Fi chip, What, Why and How? ‎[1,168 bytes]
91. (hist) ‎Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon ‎[1,166 bytes]
92. (hist) ‎How many designs can you fit on a single die ‎[1,148 bytes]
93. (hist) ‎Moving toward VexiiRiscv ‎[1,123 bytes]
94. (hist) ‎Mixed-signal system modelling and simulation ‎[1,030 bytes]
95. (hist) ‎The road to fully open hardware mobile computing ‎[1,005 bytes]
96. (hist) ‎A progressive introduction to memory bus interconnect API in Software-Defined Hardware ‎[971 bytes]
97. (hist) ‎TinyTapeout - what happened and next steps ‎[967 bytes]
98. (hist) ‎GAUT - A Free and Open-Source High-Level Synthesis tool ‎[959 bytes]
99. (hist) ‎CERN OHL v2 draft ‎[954 bytes]
100. (hist) ‎Wiki/openic ‎[902 bytes]
101. (hist) ‎A Yosys plugin for logic locking ‎[901 bytes]
102. (hist) ‎Learning hardware design in the video game Minecraft ‎[873 bytes]
103. (hist) ‎Open (and Closed) Source Analog Design with Hdl21 & VLSIR ‎[847 bytes]
104. (hist) ‎Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology ‎[840 bytes]
105. (hist) ‎Wishbone: a free SoC bus family ‎[840 bytes]
106. (hist) ‎LibreCell ‎[831 bytes]
107. (hist) ‎OpenROAD ‎[826 bytes]
108. (hist) ‎FSiC2021 ‎[825 bytes]
109. (hist) ‎LibrEDA - digital place-and-route framework from scratch ‎[819 bytes]
110. (hist) ‎CMOS functional abstraction ‎[811 bytes]
111. (hist) ‎Main Page ‎[789 bytes]
112. (hist) ‎Free Silicon Foundation ‎[787 bytes]
113. (hist) ‎Gnu Circuit Analysis Package (GnuCap) ‎[785 bytes]
114. (hist) ‎Toward multi-language open-source HDL simulation ‎[779 bytes]
115. (hist) ‎OpenSource PDK - A key enabler to unlock the potential of an open source design flow ‎[772 bytes]
116. (hist) ‎Open Source in Healthcare, an hardware approach: the echOpen project case ‎[772 bytes]
117. (hist) ‎Naja: project updates and netlist splitting tool ‎[760 bytes]
118. (hist) ‎ASICone. Goals, timeline, participants and tools ‎[722 bytes]
119. (hist) ‎The Alliance/Coriolis design flow ‎[672 bytes]
120. (hist) ‎Coriolis (tutorials) ‎[668 bytes]

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