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Showing below up to 50 results in range #31 to #80.
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- (hist) The development of the NSXLIB standard cell scalable library [2,529 bytes]
- (hist) VACASK: a Verilog-A Circuit Analysis Kernel [2,356 bytes]
- (hist) KLayout XSection tool - Deep insights or nonsense in colors? [2,351 bytes]
- (hist) Verilog-AMS in Gnucap (2024) [2,317 bytes]
- (hist) Degate: The stakes and challenges of silicon reverse engineering [2,280 bytes]
- (hist) Coriolis (installation) [2,232 bytes]
- (hist) Guidelines for speakers [2,218 bytes]
- (hist) Horizon 2021 Coordination and Support Action (CSA) proposal [2,186 bytes]
- (hist) Proof-of-concept for scalable analog blocks using the PDKMaster framework [2,164 bytes]
- (hist) KQCircuits – open-source EDA software for designing chips with super conducting qubits [2,158 bytes]
- (hist) Inclusive Modeling with SysMD [2,143 bytes]
- (hist) Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design [2,058 bytes]
- (hist) Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes [2,043 bytes]
- (hist) Verilog-A Circuit Analysis Kernel (VACASK) [2,000 bytes]
- (hist) FSiC2019 venue [1,982 bytes]
- (hist) Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana [1,950 bytes]
- (hist) Environmental impacts of electronics and the role of open source hardware [1,879 bytes]
- (hist) E-Waste Reverse Engineering Toolkit (RET) [1,844 bytes]
- (hist) 65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview [1,835 bytes]
- (hist) The Raven chip: First-time silicon success with qflow and efabless [1,824 bytes]
- (hist) Open source Design Flow status and roadmap for IHP BiCMOS technology [1,823 bytes]
- (hist) Converting 45nm transistor netlists to open standards [1,798 bytes]
- (hist) OpenRAM: An Open-Source Memory Compiler [1,792 bytes]
- (hist) Generating DRC Runsets for IHP's OpenPDK - Lessons Learned [1,756 bytes]
- (hist) Toward a collaborative environment for Open Hardware Design [1,735 bytes]
- (hist) Tutorial and FAQ on physical verification, DRC+LVS [1,728 bytes]
- (hist) OpenEPDA: photonic PDKs with open standards [1,720 bytes]
- (hist) Teaching Chip Design with Open-Source Tools [1,610 bytes]
- (hist) TestPageX [1,585 bytes]
- (hist) Standard-cell recognition [1,543 bytes]
- (hist) Mixing software abstractions for high-level FPGA programming [1,540 bytes]
- (hist) The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies [1,536 bytes]
- (hist) Recent Developments from YosysHQ [1,505 bytes]
- (hist) Black-tie Python: Formal verification with Amaranth [1,472 bytes]
- (hist) Software-Defined Hardware: Digital Design in the 21st Century with Chisel [1,463 bytes]
- (hist) Go2async: A high-level synthesis tool for asynchronous circuits [1,456 bytes]
- (hist) CACE: Defining an open-source analog and mixed-signal design flow [1,451 bytes]
- (hist) Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry? [1,447 bytes]
- (hist) Naja: an open source framework for EDA post synthesis flow development [1,445 bytes]
- (hist) PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries [1,440 bytes]
- (hist) KLayout's deep verification base project [1,423 bytes]
- (hist) Exploring open hardware solutions for ensuring the security of RISC-V processors [1,405 bytes]
- (hist) Open Source for Sustainable and Long lasting Phones [1,401 bytes]
- (hist) Caravel Panamax: The Next Generation [1,400 bytes]
- (hist) From CMOS transistors to filters - A library of analog schematics with automated sizing [1,381 bytes]
- (hist) Revolutionize your chip design with GDSFactory and Open Source PDKs [1,371 bytes]
- (hist) All you ever wanted to know about side-channel attacks and protections (and a forthcoming book) [1,365 bytes]
- (hist) Whom do you trust?: Validating process parameters for open-source tools [1,363 bytes]
- (hist) Porting software to hardware using XLS and open source PDKs [1,321 bytes]
- (hist) Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites [1,271 bytes]