Difference between revisions of "FSiC2024"
Jump to navigation
Jump to search
(Preliminary program) |
(→News) |
||
| (46 intermediate revisions by 12 users not shown) | |||
| Line 6: | Line 6: | ||
|location = Paris, Sorbonne Université | |location = Paris, Sorbonne Université | ||
|country = France | |country = France | ||
|website = [https://wiki.f-si.org/index.php/ | |website = [https://wiki.f-si.org/index.php/FSiC2024 wiki.f-si.org/index.php/FSiC2024] | ||
}} | }} | ||
| Line 13: | Line 13: | ||
== News == | == News == | ||
* June 18: On the day before FSiC, in the same room, there will be a [https://wiki.goit-project.eu/index.php?title=Open-source_silicon_and_EDA_workshop_2024 workshop on open-source silicon and open-source EDA]. Feel free to register. | |||
* May 14: [https://wiki.goit-project.eu/index.php?title=Open-source_silicon_and_EDA_workshop_2024 Webinar on open-source silicon and open-source EDA] introducing the workshop on June 18. The webinar will take place on BigBlueButton. The event is open to everybody but registration is required. | |||
= | * May 1: Submissions are closed. | ||
* January 15: Submissions are open. | |||
== Participation == | == Participation == | ||
Participation to the conference is '''free of charge''' but the attendance must be reserved per email at fsic2024 'at' f-si.org. Details will be announced on this page and over the [https://mastodon.f-si.org/@fsi mastodon channel]. | Participation to the conference is '''free of charge''' but the attendance must be reserved per email at fsic2024 'at' f-si.org. Details will be announced on this page and over the [https://mastodon.f-si.org/@fsi mastodon channel]. | ||
== Tentative program == | |||
===Before FSiC: Workshop on open-source silicon and open-source EDA=== | |||
On the day before the conference, on June 18, and in the same room, there will be a [https://wiki.goit-project.eu/index.php?title=Open-source_silicon_and_EDA_workshop_2024 workshop on open-source silicon and open-source EDA]. The discussion will lead to the creation of Working Groups and to the drafting of a Roadmap for the European Commission. Attendance is free, but [https://ec.europa.eu/eusurvey/runner/88275dc0-9321-bdeb-3d93-83ec342b6353 registration] is required. | |||
===June 19, Wednesday (day 1)=== | |||
* 8:00-9:20, Registration and coffee | |||
* 9:20, Welcome and introductory announcements | |||
==== Keynote speech ==== | |||
* 9:30, Matthew Venn ([https://www.yosyshq.com/ YosysHQ], [https://www.tinytapeout.com/ Tiny Tapeout]), ''[[The long tail of semiconductors - Education, Tools and Artisanal ASICs]]'' | |||
====High-level design and logic-synthesis==== | |||
* 10:00, Alessandro Tempia Calvino ([https://people.epfl.ch/alessandro.tempiacalvino/?lang=en EPFL]), ''[[The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies]]'' | |||
* 10:30, Tristan Gingold ([http://ghdl.free.fr/ GHDL]), ''[[How to debug a simulation?]]'' | |||
* 10:50, Martijn Bastiaan and Lucas ([https://qbaylogic.com Qbaylogic]), ''[[It's nice to have a choice: using Haskell for circuit design]]'' | |||
* 11:10, Stefano Minigutti ([https://syosil.com/ SyoSil]), ''[[Open-Source Verification of Digital ASIC/FPGA Circuits]]'' | |||
* 11:30, Charles Papon ([https://github.com/SpinalHDL SpinalHDL]), ''[[Moving toward VexiiRiscv]]'' | |||
* '''12:00-13:30''', '''lunch break''' | |||
* 13:30, Rajit Manohar ([https://yale.edu Yale]), ''[[The ACT EDA flow for asynchronous logic]]'' | |||
====Foundries and PDKs==== | |||
* 13:50, Rene Scholz, Sergei Andreev, Krzysztof Herman ([https://www.ihp-microelectronics.com IHP Microelectronics]), ''[[Update on IHP open source PDK initiative & how to submit free open source designs in IHP technology]]'' | |||
* 14:20, Sergei Andreev, T. Zecha, Krzysztof Herman ([https://www.ihp-microelectronics.com IHP Microelectronics]), ''[[IHP open source PDK: KLayout Pycell Development status]]'' | |||
* 14:40, Joaquin Matres Abril (Google), ''[[Revolutionize your chip design with GDSFactory and Open Source PDKs]]'' | |||
====On-going FOS silicon projects==== | |||
* 15:00, Matthew Venn ([https://www.yosyshq.com/ YosysHQ], [https://www.tinytapeout.com/ Tiny Tapeout]), ''[[Mixed signal support on Tiny Tapeout]]'' | |||
* 15:30, Tim Edwards ([https://efabless.com/ Efabless], [http://opencircuitdesign.com/ Open Circuit Design]), ''[[Caravel Panamax: The Next Generation]]'' | |||
* '''16:00-16:30''', '''Afternoon break.''' Coffee is served on-campus | |||
* 16:30, Philippe Sauter and Thomas Benz ([https://www.ethz.ch/ ETH Zurich]), ''[[Achieving Competitive Performance with Open EDA Tools on a 2MGE Open-Source Linux-Capable RISC-V SoC]]'' | |||
* 16:50, Xianjun Jiao ([https://github.com/open-sdr IMEC, OpenWiFi project]), ''[[An opensource Wi-Fi chip, What, Why and How? ]]'' | |||
* 17:20, Jorge Marin and Christian Rojas ([https://ac3e.usm.cl/ AC3E - Chile]), ''[[Unlocking the power: energy management open-source analog building blocks from concept to silicon-proven IP]]'' | |||
* 17:40, Jelle Verest ([https://www.tue.nl/en/ student at TU Eindhoven]), ''[[Working towards FOSS RF IC design in SKY130]]'' | |||
* 18:00, Staf Verhaegen ([https://www.chips4makers.io/blog Chips4Makers]), ''[[Project Arrakeen: a PDKMaster based framework for scalable and portable digital and analog circuits]]'' | |||
====Workshop==== | |||
* 18:20-19:00, technical discussion | |||
===June 20, Thursday (day 2)=== | |||
* 8:00-8:40, Early bird coffee and tea | |||
====Analog flow, transistor modelling and circuit simulation==== | |||
* 8:40, Leo Moser and Tim Edwards ([https://efabless.com/ Efabless]), ''[[CACE: Defining an open-source analog and mixed-signal design flow]]'' | |||
* 9:10, Arpad Buermen ([https://fides.fe.uni-lj.si/~arpadb/cv/cv2024.pdf University of Ljubljana]), ''[[VACASK: a Verilog-A Circuit Analysis Kernel]]'' | |||
* 9:30, Felix Salfelder ([https://nlnet.nl/project/Gnucap-MixedSignals/ Gnucap MixedSignals]), ''[[Verilog-AMS in Gnucap (2024)|Verilog-AMS in Gnucap]]'' | |||
* 9:50, Arpad Buermen ([https://fides.fe.uni-lj.si/~arpadb/cv/cv2024.pdf University of Ljubljana]), ''[[PyOpus - a Python library for design automation]]'' | |||
* 10:10, Deni Alves ([https://deel.ufsc.br/ Federal University of Santa Catarina - Brasil]), ''[[ACM2 – A design-oriented model for open-source tools]]'' | |||
* 10:35, Wladek Grabinski, ([https://www.mos-ak.org/wg.html MOS-AK]), ''[[FOSS EKV3 Charge-based MOS Transistor Model: an Engineering and Educational Tool]]'' | |||
====Hardware security==== | |||
* 10:40, Dorian Bachelot ([https://www.degate.org/ Degate]), ''[[Degate: The stakes and challenges of silicon reverse engineering]]'' | |||
* 11:10, Roselyne Chotin and Gabriel Gouvine ([http://lip6.fr/ LIP6]), ''[[Moosic: Writing a Yosys Plugin for Design for Trust]]'' | |||
* 11:40, Julien Béguinot ([https://www.telecom-paris.fr/ Télécom Paris]), Wei Cheng ([https://www.secure-ic.com/ Secure-IC], [https://www.telecom-paris.fr/ Télécom Paris]), Sylvain Guilley ([https://www.secure-ic.com/ Secure-IC]) and Olivier Rioul ([https://www.telecom-paris.fr/ Télécom Paris]), ''[[Tight side-channel security bounds on hardware cryptographic engines]]'' | |||
* '''12:00-13:30''', '''lunch break''' | |||
====Policy, EU projects and funding opportunities==== | |||
* 13:30, Korbinian Schreiber and Tina Tauchnitz ([https://vdivde-it.de VDI/VDE-IT]), ''[[German Microelectronics Design Initiative]]'' | |||
* 14:00, Luca Pezzarossa ([https://orbit.dtu.dk/en/persons/luca-pezzarossa DTU]), ''[[From Theory to Tape-Out: Chip Design Education with Edu4Chip ]]'' | |||
* 14:20, Helio Fernandez Tellez ([https://www.imec-int.com/en imec]), ''[[EUROPRACTICE's Catalog and IP Sharing Program]]'' | |||
* 14:35, Michiel Leenaars ([https://nlnet.nl/ NLnet Foundation]), ''[[2024-Talk-MichielLeenaars | Update on libre silicon and OSHW related efforts within NGI and NLnet]]'' | |||
====Standards==== | |||
* 14:40, Pieter Hijma ([https://opentoolchain.org/ Open Toolchain Foundation]), ''[[Open Documentation Standards and Open Toolchains]]'' | |||
* 15:00, Philippe Morey-Chaisemartin ([https://xyalis.com/ Xyalis]/OASIS), ''[[Beyond tape-out: open the dark side]]'' | |||
* '''15:30-16:00''', '''Afternoon break.''' Coffee is served on-campus | |||
====Sustainability session==== | |||
16:00-19:00: This session is organized independently by Sorbonne Université. | |||
The program is available [https://largo.lip6.fr/en/events/ here]. | |||
===June 21, Friday (day 3)=== | |||
* 8:00-9:00, Early bird coffee and tea | |||
==== Keynote speech ==== | |||
* 9:00, Andrew Kahng ([https://openroadinitiative.org/ OpenROAD Initiative]), ''[[OpenROAD and The OpenROAD Initiative: Foundations for Open Innovation]]'' | |||
====Back-end design tools==== | |||
* 9:30, Juhani Kataja ([https://www.csc.fi/home CSC]), ''[[Simulating electromagnetics with ElmerFEM]]'' | |||
* 10:00, Mohamed Gaber ([https://aucegypt.edu student at AUC]), ''[[Fault, Open-Source EDA's Missing DFT Toolchain]]'' | |||
* 10:30, Gabriel Gouvine ([http://lip6.fr/ LIP6]), ''[[Quaigh: open source test pattern generation]]'' | |||
* 11:30, Andreas Krinke ([https://www.ifte.de/english/staff/krinke.html TU Dresden]), ''[[Generating DRC Runsets for IHP's OpenPDK - Lessons Learned]]'' | |||
* '''12:00-13:30''', '''lunch break''' | |||
* 13:30, Dario Quintero ([https://piel.readthedocs.io/en/latest/sections/microservices/index.html PIEL]), ''[[Integrating Mixed-Signal Microelectronics and Photonics: A Co-Design Approach with Piel]]'' | |||
* 13:50, Christophe Alexandre ([https://github.com/xtofalex/naja Naja]), ''[[naja_edit: An Open Source Tool for Gate-Level Netlist Optimization and Editing]]'' | |||
* 14:10, Tobias Senti ([https://www.ethz.ch/ student at ETH Zurich]), ''[[Liberty74: An Open-Source Verilog-to-PCB Flow]]'' | |||
* 14:30, Ali Oudrhiri ([http://lip6.fr/ LIP6]), ''[[Circuit design with Open EDA tools: a case study]]'' | |||
* 14:50, Mazher Iqbal ([http://lip6.fr/ LIP6]), ''[[Accessibility and availability of Open EDA tools: the nightmare of distributions’ dependencies]]'' | |||
* 15:10 Conclusions | |||
== Practical information == | |||
*[[FSiC2024 venue|Venue, map, hotels]] | |||
*[[Guidelines for speakers]] | |||
== Organizing committee == | == Organizing committee == | ||
| Line 97: | Line 192: | ||
<div>https://www.imm.dtu.dk/~masca/</div> | <div>https://www.imm.dtu.dk/~masca/</div> | ||
</div> | </div> | ||
<div style="display:table-cell; padding-left: 2rem; text-align: center; vertical-align: middle;"><nowiki> | <div style="display:table-cell; padding-left: 2rem; text-align: center; vertical-align: middle;"><nowiki>‟Open-source tools and technology gives freedom to students to explore chip design on their own and on their computers, not limiting them to the walled garden of a dedicated lab at the University”</nowiki></div> | ||
</div> | </div> | ||
| Line 103: | Line 198: | ||
</div> | </div> | ||
==Local hosting committee== | ==Local hosting committee== | ||
| Line 155: | Line 205: | ||
We are looking for sponsors to cover extra services at the conference, such as food and beverages. In case of interest, please write at fsic2024 'at' f-si.org. | We are looking for sponsors to cover extra services at the conference, such as food and beverages. In case of interest, please write at fsic2024 'at' f-si.org. | ||
== | ==Sponsors== | ||
[[File:IHP_Microelectronics.png|180px|link=https://www.ihp-microelectronics.com/]] | |||
[[File:SUS_LIP6_CNRSnew.jpg|500px|link=https://www.lip6.fr]] | [[File:SUS_LIP6_CNRSnew.jpg|500px|link=https://www.lip6.fr]] | ||
[[File:irill.png|300px|link=https://www.irill.org]] | [[File:irill.png|300px|link=https://www.irill.org]] | ||
[[File:cemip-logo.png|250px|link=https://sciences.sorbonne-universite.fr/faculte/ufr-instituts-observatoires-ecoles/ufr-dingenierie/plateformes-ingenierie/le-cemip-centre]] | [[File:cemip-logo.png|250px|link=https://sciences.sorbonne-universite.fr/faculte/ufr-instituts-observatoires-ecoles/ufr-dingenierie/plateformes-ingenierie/le-cemip-centre]] | ||
[[File:DTU Logo.jpg|180px|link=dtu.dk]] | |||
==Acknowledgements== | ==Acknowledgements== | ||
This conference is funded by the | This conference is funded by European Union through the Coordination and Support Action [https://goit-project.eu GoIT] project with ID number 101070669. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or of the European Commission. Neither the European Union nor the European Commission can be held responsible for them. | ||
[[File:EU-co-funded.jpg|500px|link=https://ec.europa.eu/info/funding-tenders/opportunities/portal/screen/opportunities/topic-details/horizon-cl4-2021-digital-emerging-01-05]] | [[File:EU-co-funded.jpg|500px|link=https://ec.europa.eu/info/funding-tenders/opportunities/portal/screen/opportunities/topic-details/horizon-cl4-2021-digital-emerging-01-05]] | ||
[[File:GoIT.png|300px|link=https://goit-project.eu]] | [[File:GoIT.png|300px|link=https://goit-project.eu]] | ||
This conference also received funding from the Swiss State Secretariat for Education, Research and Innovation (SERI) under the [https://nlnet.nl/commonsfund/ NGI0 Commons Fund] project. The NGI0 Commons Fund has received funding from the European Union’s Horizon Europe research and innovation programme under grant agreement No. 101135429. | |||
[[File:WBF SBFI EU Frameworkprogramme E RGB pos quer.png|500px|alt=Funded by SERI logo]] | |||
[[File:NGI0 tag.svg|500px|alt=NGI Zero Logo]] | |||
Latest revision as of 11:13, 28 November 2024
| Free Silicon Conference 2024 | |
|---|---|
 | |
| Genre | Free software and free hardware development conference |
| Location(s) | Paris, Sorbonne Université |
| Country | France |
| Website | wiki.f-si.org/index.php/FSiC2024 |
The 2024 Free Silicon Conference (FSiC) will take place in Paris (Sorbonne) on June 19, 20, 21 2024 (Wednesday to Friday). This event will build on top of the past FSiC editions. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere.
News
- June 18: On the day before FSiC, in the same room, there will be a workshop on open-source silicon and open-source EDA. Feel free to register.
- May 14: Webinar on open-source silicon and open-source EDA introducing the workshop on June 18. The webinar will take place on BigBlueButton. The event is open to everybody but registration is required.
- May 1: Submissions are closed.
- January 15: Submissions are open.
Participation
Participation to the conference is free of charge but the attendance must be reserved per email at fsic2024 'at' f-si.org. Details will be announced on this page and over the mastodon channel.
Tentative program
Before FSiC: Workshop on open-source silicon and open-source EDA
On the day before the conference, on June 18, and in the same room, there will be a workshop on open-source silicon and open-source EDA. The discussion will lead to the creation of Working Groups and to the drafting of a Roadmap for the European Commission. Attendance is free, but registration is required.
June 19, Wednesday (day 1)
- 8:00-9:20, Registration and coffee
- 9:20, Welcome and introductory announcements
Keynote speech
- 9:30, Matthew Venn (YosysHQ, Tiny Tapeout), The long tail of semiconductors - Education, Tools and Artisanal ASICs
High-level design and logic-synthesis
- 10:00, Alessandro Tempia Calvino (EPFL), The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies
- 10:30, Tristan Gingold (GHDL), How to debug a simulation?
- 10:50, Martijn Bastiaan and Lucas (Qbaylogic), It's nice to have a choice: using Haskell for circuit design
- 11:10, Stefano Minigutti (SyoSil), Open-Source Verification of Digital ASIC/FPGA Circuits
- 11:30, Charles Papon (SpinalHDL), Moving toward VexiiRiscv
- 12:00-13:30, lunch break
- 13:30, Rajit Manohar (Yale), The ACT EDA flow for asynchronous logic
Foundries and PDKs
- 13:50, Rene Scholz, Sergei Andreev, Krzysztof Herman (IHP Microelectronics), Update on IHP open source PDK initiative & how to submit free open source designs in IHP technology
- 14:20, Sergei Andreev, T. Zecha, Krzysztof Herman (IHP Microelectronics), IHP open source PDK: KLayout Pycell Development status
- 14:40, Joaquin Matres Abril (Google), Revolutionize your chip design with GDSFactory and Open Source PDKs
On-going FOS silicon projects
- 15:00, Matthew Venn (YosysHQ, Tiny Tapeout), Mixed signal support on Tiny Tapeout
- 15:30, Tim Edwards (Efabless, Open Circuit Design), Caravel Panamax: The Next Generation
- 16:00-16:30, Afternoon break. Coffee is served on-campus
- 16:30, Philippe Sauter and Thomas Benz (ETH Zurich), Achieving Competitive Performance with Open EDA Tools on a 2MGE Open-Source Linux-Capable RISC-V SoC
- 16:50, Xianjun Jiao (IMEC, OpenWiFi project), An opensource Wi-Fi chip, What, Why and How?
- 17:20, Jorge Marin and Christian Rojas (AC3E - Chile), Unlocking the power: energy management open-source analog building blocks from concept to silicon-proven IP
- 17:40, Jelle Verest (student at TU Eindhoven), Working towards FOSS RF IC design in SKY130
- 18:00, Staf Verhaegen (Chips4Makers), Project Arrakeen: a PDKMaster based framework for scalable and portable digital and analog circuits
Workshop
- 18:20-19:00, technical discussion
June 20, Thursday (day 2)
- 8:00-8:40, Early bird coffee and tea
Analog flow, transistor modelling and circuit simulation
- 8:40, Leo Moser and Tim Edwards (Efabless), CACE: Defining an open-source analog and mixed-signal design flow
- 9:10, Arpad Buermen (University of Ljubljana), VACASK: a Verilog-A Circuit Analysis Kernel
- 9:30, Felix Salfelder (Gnucap MixedSignals), Verilog-AMS in Gnucap
- 9:50, Arpad Buermen (University of Ljubljana), PyOpus - a Python library for design automation
- 10:10, Deni Alves (Federal University of Santa Catarina - Brasil), ACM2 – A design-oriented model for open-source tools
- 10:35, Wladek Grabinski, (MOS-AK), FOSS EKV3 Charge-based MOS Transistor Model: an Engineering and Educational Tool
Hardware security
- 10:40, Dorian Bachelot (Degate), Degate: The stakes and challenges of silicon reverse engineering
- 11:10, Roselyne Chotin and Gabriel Gouvine (LIP6), Moosic: Writing a Yosys Plugin for Design for Trust
- 11:40, Julien Béguinot (Télécom Paris), Wei Cheng (Secure-IC, Télécom Paris), Sylvain Guilley (Secure-IC) and Olivier Rioul (Télécom Paris), Tight side-channel security bounds on hardware cryptographic engines
- 12:00-13:30, lunch break
Policy, EU projects and funding opportunities
- 13:30, Korbinian Schreiber and Tina Tauchnitz (VDI/VDE-IT), German Microelectronics Design Initiative
- 14:00, Luca Pezzarossa (DTU), From Theory to Tape-Out: Chip Design Education with Edu4Chip
- 14:20, Helio Fernandez Tellez (imec), EUROPRACTICE's Catalog and IP Sharing Program
- 14:35, Michiel Leenaars (NLnet Foundation), Update on libre silicon and OSHW related efforts within NGI and NLnet
Standards
- 14:40, Pieter Hijma (Open Toolchain Foundation), Open Documentation Standards and Open Toolchains
- 15:00, Philippe Morey-Chaisemartin (Xyalis/OASIS), Beyond tape-out: open the dark side
- 15:30-16:00, Afternoon break. Coffee is served on-campus
Sustainability session
16:00-19:00: This session is organized independently by Sorbonne Université.
The program is available here.
June 21, Friday (day 3)
- 8:00-9:00, Early bird coffee and tea
Keynote speech
- 9:00, Andrew Kahng (OpenROAD Initiative), OpenROAD and The OpenROAD Initiative: Foundations for Open Innovation
Back-end design tools
- 9:30, Juhani Kataja (CSC), Simulating electromagnetics with ElmerFEM
- 10:00, Mohamed Gaber (student at AUC), Fault, Open-Source EDA's Missing DFT Toolchain
- 10:30, Gabriel Gouvine (LIP6), Quaigh: open source test pattern generation
- 11:30, Andreas Krinke (TU Dresden), Generating DRC Runsets for IHP's OpenPDK - Lessons Learned
- 12:00-13:30, lunch break
- 13:30, Dario Quintero (PIEL), Integrating Mixed-Signal Microelectronics and Photonics: A Co-Design Approach with Piel
- 13:50, Christophe Alexandre (Naja), naja_edit: An Open Source Tool for Gate-Level Netlist Optimization and Editing
- 14:10, Tobias Senti (student at ETH Zurich), Liberty74: An Open-Source Verilog-to-PCB Flow
- 14:30, Ali Oudrhiri (LIP6), Circuit design with Open EDA tools: a case study
- 14:50, Mazher Iqbal (LIP6), Accessibility and availability of Open EDA tools: the nightmare of distributions’ dependencies
- 15:10 Conclusions
Practical information
Organizing committee
‟Technology is political. I stand for defending free access to technology and the right for transparency.”
‟Free and transparent technology empowers people and protects fundamental freedoms.”
Constantin Gierczak-Galle
Student and enthousiast
‟Technology can be both Mankind's development and demise. Promoting the former while hindering the latter can only happen through decentralization, democratization and open collaboration.”
‟I am passionate about helping people with my technical skills. Coding EDA is like gardening to me: may it grow and feed people.”
‟I like to understand technology, to adapt and enhance it. Technology should not be mythical or owned by experts only, it needs to be comprehensible.”
‟Open-source tools and technology gives freedom to students to explore chip design on their own and on their computers, not limiting them to the walled garden of a dedicated lab at the University”
Local hosting committee
The event is hosted by Sorbonne Université (SU) and members of the LIP6 laboratory including Cécile Braunstein, Roselyne Chotin, Marie-Minerve Louerat and Franck Wajsbürt.
Donations
We are looking for sponsors to cover extra services at the conference, such as food and beverages. In case of interest, please write at fsic2024 'at' f-si.org.
Sponsors
Acknowledgements
This conference is funded by European Union through the Coordination and Support Action GoIT project with ID number 101070669. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or of the European Commission. Neither the European Union nor the European Commission can be held responsible for them.
This conference also received funding from the Swiss State Secretariat for Education, Research and Innovation (SERI) under the NGI0 Commons Fund project. The NGI0 Commons Fund has received funding from the European Union’s Horizon Europe research and innovation programme under grant agreement No. 101135429.
