Dead-end pages
Jump to navigation
Jump to search
The following pages do not link to other pages in F-Si wiki.
Showing below up to 64 results in range #1 to #64.
View (previous 100 | next 100) (20 | 50 | 100 | 250 | 500)
- ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals
- A Yosys plugin for logic locking
- A progressive introduction to memory bus interconnect API in Software-Defined Hardware
- Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks
- All you ever wanted to know about side-channel attacks and protections (and a forthcoming book)
- An overview of libre silicon and OSHW related efforts within NGI and NLnet
- Black-tie Python: Formal verification with Amaranth
- CERN Open Hardware License (OHL)
- CIAN Team Welcome
- CMOS functional abstraction
- Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry?
- Composing an out-of-order CPU using software technics
- Converting 45nm transistor netlists to open standards
- Coriolis (installation)
- Coriolis (tutorials)
- Coriolis a RTL to GDSII FOSS Design Flow
- Degate: The stakes and challenges of silicon reverse engineering
- E-Waste Reverse Engineering Toolkit (RET)
- F-Si Donations
- F-Si Statute
- FSiC2019 reimbursement
- FSiC2019 venue
- FSiC2020
- FSiC2021
- FSiC2022 venue
- FSiC2023 venue
- FSiC2024 venue
- From CMOS transistors to filters - A library of analog schematics with automated sizing
- From Theory to Tape-Out: Chip Design Education with Edu4Chip
- GAUT
- Guidelines for speakers
- Horizon 2021 Coordination and Support Action (CSA) proposal
- How to foster GreenIT through open hardware?
- LIP6 Welcome
- Learning hardware design in the video game Minecraft
- Libre Silicon Compiler
- Matthias:UnsortedThroughsOnFOSSForEDA
- Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design
- Need for a free alternative to OpenAccess (by Matthias)
- Open-source electronic design automation for agile network defense at OVHcloud
- OpenROAD
- Open (and Closed) Source Analog Design with Hdl21 & VLSIR
- Open Source for Sustainable and Long lasting Phones
- Open Source in Healthcare, an hardware approach: the echOpen project case
- Open source Design Flow status and roadmap for IHP BiCMOS technology
- PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries
- Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites
- Proof-of-concept for scalable analog blocks using the PDKMaster framework
- Recommendations and roadmap for the development of open-source silicon in the EU
- Recommendations for the EC on how to reduce the environmental impact of the ICT sector
- Revolutionize your chip design with GDSFactory and Open Source PDKs
- Statute of the Free Silicon Foundation (I) ETS
- The ACT EDA flow for asynchronous logic
- The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies
- The development of the NSXLIB standard cell scalable library
- The open-source and low-cost echo-stethoscope project
- Toward a collaborative environment for Open Hardware Design
- VACASK: a Verilog-A Circuit Analysis Kernel
- Verilog-AMS in Gnucap
- Verilog-AMS in Gnucap (2024)
- Verilog-A Circuit Analysis Kernel (VACASK)
- White paper for the EC, January 2020
- Wiki/openic
- XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design