Pages with the most revisions

Showing below up to 50 results in range #21 to #70.

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21. Inclusive Modeling with SysMD‏‎ (13 revisions)
22. From filters to CMOS transistors - A library of analog schematics with automated sizing‏‎ (12 revisions)
23. VACASK: a Verilog-A Circuit Analysis Kernel‏‎ (12 revisions)
24. Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana‏‎ (10 revisions)
25. FSiC2019 venue‏‎ (10 revisions)
26. Mixing software abstractions for high-level FPGA programming‏‎ (10 revisions)
27. Teaching Chip Design with Open-Source Tools‏‎ (10 revisions)
28. Software-Defined Hardware: Digital Design in the 21st Century with Chisel‏‎ (9 revisions)
29. Open Source Parasitic Extraction‏‎ (9 revisions)
30. LibreCell‏‎ (9 revisions)
31. Merging Gnucap and Qucs -- The Why and How‏‎ (8 revisions)
32. Wiki/openic‏‎ (8 revisions)
33. KLayout XSection tool - Deep insights or nonsense in colors?‏‎ (8 revisions)
34. Need for a free alternative to OpenAccess (by Matthias)‏‎ (8 revisions)
35. Environmental impacts of electronics and the role of open source hardware‏‎ (8 revisions)
36. The development of the NSXLIB standard cell scalable library‏‎ (8 revisions)
37. Standard-cell synthesis‏‎ (8 revisions)
38. Mixed-signal system modelling and simulation‏‎ (8 revisions)
39. FSiC2023 venue‏‎ (8 revisions)
40. Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology‏‎ (7 revisions)
41. Toward a collaborative environment for Open Hardware Design‏‎ (7 revisions)
42. Coriolis (installation)‏‎ (7 revisions)
43. Gnu Circuit Analysis Package (GnuCap)‏‎ (7 revisions)
44. TinyTapeout - what happened and next steps‏‎ (7 revisions)
45. Challenge to Fabricate LSI without NDA with Open Method‏‎ (7 revisions)
46. Verilog-A Circuit Analysis Kernel (VACASK)‏‎ (7 revisions)
47. FSiC2021‏‎ (7 revisions)
48. KQCircuits – open-source EDA software for designing chips with super conducting qubits‏‎ (7 revisions)
49. Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks‏‎ (6 revisions)
50. The Alliance/Coriolis design flow‏‎ (6 revisions)
51. GHDL and the economy of EDA FOSS‏‎ (6 revisions)
52. F8‏‎ (6 revisions)
53. The importance of EU Academia in developing the chips of the future‏‎ (6 revisions)
54. ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals‏‎ (6 revisions)
55. GAUT - A Free and Open-Source High-Level Synthesis tool‏‎ (6 revisions)
56. Black-tie Python: Formal verification with Amaranth‏‎ (6 revisions)
57. LibrEDA - digital place-and-route framework from scratch‏‎ (6 revisions)
58. Exploring open hardware solutions for ensuring the security of RISC-V processors‏‎ (5 revisions)
59. Tutorial and FAQ on physical verification, DRC+LVS‏‎ (5 revisions)
60. Proof-of-concept for scalable analog blocks using the PDKMaster framework‏‎ (5 revisions)
61. Learning hardware design in the video game Minecraft‏‎ (5 revisions)
62. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries‏‎ (5 revisions)
63. A Yosys plugin for logic locking‏‎ (5 revisions)
64. White paper for the EC, January 2020‏‎ (5 revisions)
65. Open source Design Flow status and roadmap for IHP BiCMOS technology‏‎ (5 revisions)
66. CERN OHL v2 draft‏‎ (5 revisions)
67. The Raven chip: First-time silicon success with qflow and efabless‏‎ (5 revisions)
68. Digital placement algorithms in Coriolis‏‎ (5 revisions)
69. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks‏‎ (5 revisions)
70. Towards digital sovereignty by open source (hardware)‏‎ (5 revisions)

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