Difference between revisions of "FSiC2023"

Free Silicon Conference 2023
Genre	Free software and free hardware development conference
Location(s)	Paris, Sorbonne Université, Campus Pierre et Marie Curie, 4 Place Jussieu
Country	France
Website	wiki.f-si.org/index.php/FSiC2023

Latest revision as of 17:08, 1 October 2023

The 2023 Free Silicon Conference (FSiC) took place in Paris (Sorbonne Université, 4 Place Jussieu, Paris) on July 10,11,12 2023 (Monday to Wednesday). This event was built on top of the past FSiC2019 and FSiC2022 editions. The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification.

News

July 28: Most videos are now available on PeerTube.

Objectives and motto

The goal of FSiC is to make the technology accessible to small businesses, startups, universities and schools. Students, makers and professional should have direct access to education, without barriers, paywalls and legal burdens. What's the value of multi-billion public investments if there aren't designers, engineers and other experts who can operate the industry and who master the tools to innovate? We all took apart watches and radios when we were kids, hence we learned how they work. It is time to look inside chips and their tool-chains so that we can study, improve, repair and trust them.

The conference motto is therefore: Education, sustainability and innovation by openness and collaboration!

Submission

For proposing a talk, please submit a title and a short summary at fsic2023 'at' f-si.org before June 15.

Participation

Lunches and coffee breaks are offered, funded by the EU HORIZON Coordination and Support Action GoIT project with ID number 101070669.

Participation to the conference is free of charge but the attendance must be reserved per email at fsic2023 'at' f-si.org for local organization BEFORE the conference. Details will be announced on this page and over the mastodon channel. The slides and the video recordings of the talks will be published on our website.

Organizing committee

Marie-Minerve Louerat

Scientist and Teacher

https://www-soc.lip6.fr/users/marie-minerve-louerat

‟I have a passion for educating and teaching students, to give them tools for life and learning.”

Luca Alloatti

Libre Hardware Promoter

https://orcid.org/0000-0002-1245-4179

‟Technology is political. I stand for defending free access to technology and the right for transparency.”

Thomas Kramer

Skeptical Technology Enthusiast

https://libreda.org

‟I like to understand technology, to adapt and enhance it. Technology should not be mythical or owned by experts only, it needs to be comprehensible.”

Matthias Köfferlein

FOSS EDA Author

https://www.klayout.org

‟I am passionate about helping people with my technical skills. Coding EDA is like gardening to me: may it grow and feed people.”

Conference program

July 10, Monday (Day 1)

9:00-9:30, Registration and coffee

July 11, Tuesday (Day 2)

8:30-9:30, Early bird coffee and tea

Keynote speech

9:30-10:00, Luca Weiss (Fairphone), Open Source for Sustainable and Long lasting Phones

Hardware security

10:00-10:30, Jean Bruant (OVHcloud), Open-source electronic design automation for agile network defense at OVHcloud
10:30-11:00, Gaëtan Cassiers (TU Graz), Physical security for cryptographic implementations with open hardware
11:00-11:30, Pat Deegan (Psychogenic Technologies), Black-tie Python: Formal verification with Amaranth
11:30-12:00, Pablo Navarro (Seville Institute of Microelectronics), Exploring open hardware solutions for ensuring the security of RISC-V processors
12:00-13:30, lunch break
13:30-14:00, Gabriel Gouvine (LIP6), A Yosys plugin for logic locking
14:00-14:30, Wei Cheng, Sylvain Guilley, and Olivier Rioul (Telecom Paris and Secure IC), All you ever wanted to know about side-channel attacks and protections (and a forthcoming book)

IP blocks

14:30-15:00, Manuel Moser, Patrick Fath, and Harald Pretl (Johannes Kepler University Linz), Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology

Transistor modelling and circuit simulation

15:00-15:30, Felix Salfelder (GnuCap), Verilog-AMS in Gnucap

Sustainability (part 2)

15:30-16:00, Maxime Pelcat (Univ Rennes, INSA Rennes and IETR), Environmental impacts of electronics and the role of open source hardware
16:00-16:30, Afternoon break. Coffee is served on-campus
16:30-17:00, Andrea Quilici (Resilio), How to foster GreenIT through open hardware?
17:00-17:30, Julia Hess (Stiftung Neue Verantwortung), The importance of EU Academia in developing the chips of the future
17:30-18:00, Maurits Fennis (Unbinare), E-Waste Reverse Engineering Toolkit (RET)

Funding opportunities

18:00-18:30, Michiel Leenaars (NLnet Foundation), An overview of libre silicon and OSHW related efforts within NGI and NLnet

Back-end design tools

18:30-19:00, Osama Hammad Abdel Reheem (The American university in Cairo), OpenROAD

July 12, Wednesday (Day 3)

8:30-9:30, Early bird coffee and tea

Back-end design tools

9:30-10:00, Dan Fritchman (UC Berkeley), Open (and Closed) Source Analog Design with Hdl21 & VLSIR
10:00-10:30, Christophe Alexandre (Naja), Naja: project updates and netlist splitting tool
10:30-11:00, Pavel Smirnov (IQM), KQCircuits – open-source EDA software for designing chips with super conducting qubits
11:00-11:30, Jean-Paul Chaput (LIP6, Sorbonne Université), Coriolis a RTL to GDSII FOSS Design Flow
11:30-12:00, Matthias Köfferlein (KLayout), Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks
12:00-13:30, lunch break

Teaching and education

13:30-14:00, Martin Schoeberl (DTU Compute), Teaching Chip Design with Open-Source Tools
14:00-14:30, Gabriel Doriath Döhler and Constantin Gierczak-Galle (École normale supérieure), Learning hardware design in the video game Minecraft
14:30-15:00, Johan Euphrosine (Google), Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks

Paving the road for open source flow: gaps, challenges, opportunities

15:00-15:30, open discussion
15:30-16:00, conclusions

Practical information

Donations

We are looking for sponsors to cover extra services at the conference, such as food and beverages. In case of interest, please write at fsic2023 'at' f-si.org.

Acknowledgements

This conference is funded by the EU HORIZON Coordination and Support Action GoIT project with ID number 101070669.

@@ Line 4: / Line 4: @@
 |logo              = fsic2023_logo.png
 |genre             = Free software and free hardware development conference
-|location          = Paris, Sorbonne Université
+|location          = Paris, Sorbonne Université, Campus Pierre et Marie Curie, 4 Place Jussieu
 |country           = France
 |website           = [https://wiki.f-si.org/index.php/FSiC2023 wiki.f-si.org/index.php/FSiC2023]
@@ Line 10: / Line 10: @@
-The 2023 Free Silicon Conference (FSiC) will take place in Paris (Sorbonne) on '''July 10,11,12 2022''' (Monday to Wednesday). This event will build on top of the past [https://wiki.f-si.org/index.php/FSiC2019 FSiC2019] and [https://wiki.f-si.org/index.php/FSiC2022 FSiC2022] editions. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere.
+The 2023 Free Silicon Conference (FSiC) took place in Paris (Sorbonne Université, 4 Place Jussieu, Paris) on '''July 10,11,12 2023''' (Monday to Wednesday). This event was built on top of the past [https://wiki.f-si.org/index.php/FSiC2019 FSiC2019] and [https://wiki.f-si.org/index.php/FSiC2022 FSiC2022] editions. The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification.
 == News ==
-February 16: submissions are open.
+July 28: Most videos are now available on [https://peertube.f-si.org/video-channels/fsic2023/videos PeerTube].
+== Objectives and motto ==
+The goal of FSiC is to make the technology accessible to small businesses, startups, universities and schools. Students, makers and professional should have direct access to education, without barriers, paywalls and legal burdens.
+What's the value of multi-billion public investments if there aren't designers, engineers and other experts who can operate the industry and who master the tools to innovate?
+We all took apart watches and radios when we were kids, hence we learned how they work. It is time to look inside chips and their tool-chains so that we can study, improve, repair and trust them.
+'''The conference motto is therefore''': Education, sustainability and innovation by openness and collaboration!
 == Submission ==
-For proposing a talk, please submit a title and a short summary at '''fsic2023 'at' f-si.org'''.
+For proposing a talk, please submit a title and a short summary at '''fsic2023 'at' f-si.org''' before June 15.
 == Participation ==
-Participation to the conference is '''free of charge''' but the attendance must be reserved per email at fsic2023 'at' f-si.org. Details will be announced on this page and over the mastodon channel. The slides and the video recordings of the talks will be published on our website.
+Lunches and coffee breaks are offered, funded by the EU HORIZON Coordination and Support Action [https://goit-project.eu GoIT] project with ID number 101070669.
+Participation to the conference is '''free of charge''' but the attendance must be reserved per email at fsic2023 'at' f-si.org for local organization BEFORE the conference. Details will be announced on this page and over the mastodon channel. The slides and the video recordings of the talks will be published on our website.
 == Organizing committee ==
@@ Line 79: / Line 88: @@
 </div>
-== Tentative program ==
+== Conference program ==
-===High-level design===
-===Hardware security===
+===July 10, Monday (Day 1)===
-===On-going FOS silicon projects===
+* 9:00-9:30, Registration and coffee
-===Memories===
-===Foundries and PDKs===
+====Welcome====
-===Transistor modelling===
+* 9:30-9:40, Welcome from the ([https://www.lip6.fr LIP6]), [[Welcome from LIP6|Welcome from Sorbonne Université and LIP6]]
-===Place-and-route tools===
+* 9:40-9:50, Rihards Novickis ([https://www.edi.lv/en/ EDI]), [[Introduction to the GoIT project]]
-===Parasitic extraction===
+* 9:50-10:00, Luca Alloatti ([https://f-si.org/ F-Si]), [[Welcome from the Free Silicon Foundation 2023|Welcome from the Free Silicon Foundation]]
-===Design rule checking===
-===Schematic editors===
+==== Keynote speech ====
-===Photonics===
+* 10:00-10:30, Lukas Hartmann ([https://mntre.com/ MNT Research]), ''[[The road to fully open hardware mobile computing]]''
-===Sustainability===
+====High-level design and logic-synthesis====
+* 10:30-11:00, Martin Schoeberl ([https://www.imm.dtu.dk/~masca/ DTU Compute]), ''[[Software-Defined Hardware: Digital Design in the 21st Century with Chisel]]''
+* 11:00-11:30, Charles Papon ([https://github.com/SpinalHDL SpinalHDL]), ''[[A progressive introduction to memory bus interconnect API in Software-Defined Hardware]]''
+* 11:30-12:00, Loïc Sylvestre ([https://github.com/lsylvestre/macle Macle]), ''[[Mixing software abstractions for high-level FPGA programming]]''
+* '''12:00-13:30''', '''lunch break'''
+* 13:30-14:00, Tristan Gingold ([http://ghdl.free.fr/ GHDL]), ''[[Toward multi-language open-source HDL simulation]]''
+* 14:00-14:30, N. Engelhardt ([https://www.yosyshq.com/ YosysHQ GmbH]), ''[[Recent Developments from YosysHQ]]''
+* 14:30-15:00, Benjamin Barzen ([https://github.com/berkeley-abc/abc ABC]), ''[[Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry?]]''
+* 15:00-15:30, Thomas Benz ([https://www.ethz.ch ETH Zurich]), ''[[Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana]]''
+====Foundries and PDKs====
+* 15:30-16:00, Staf Verhaegen ([https://www.chips4makers.io/blog Chips4Makers], [https://chipflow.io ChipFlow]), ''[[Proof-of-concept for scalable analog blocks using the PDKMaster framework]]''
+* '''16:00-16:30''', '''Afternoon break.''' Coffee is served on-campus
+* 16:30-17:00, Rene Scholz and Sergei Andreev ([https://www.ihp-microelectronics.com IHP Microelectronics]), ''[[Open source Design Flow status and roadmap for IHP BiCMOS technology]]''
+====On-going FOS silicon projects====
+* 17:00-17:30, Matthew Venn ([https://www.yosyshq.com/ YosysHQ], [https://www.chipflow.io/ ChipFlow]), ''[[TinyTapeout - what happened and next steps]]''
+* 17:30-18:00, Thomas Parry ([https://spherical-systems.com/ SPHERICAL]), ''[[Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites]]''
+====Sustainability (part 1)====
+* 18:00-18:45, David Bol ([https://perso.uclouvain.be/david.bol/index.html ICTEAM Institute, UC Louvain]), ''[[Analyzing open-source chip design ecosystem from an environmental sustainability perspective]]''
+===July 11, Tuesday (Day 2)===
+* 8:30-9:30, Early bird coffee and tea
+==== Keynote speech ====
+* 9:30-10:00, Luca Weiss ([https://fairphone.com/ Fairphone]), ''[[Open Source for Sustainable and Long lasting Phones]]''
+====Hardware security====
+* 10:00-10:30, Jean Bruant ([https://www.ovhcloud.com OVHcloud]), ''[[Open-source electronic design automation for agile network defense at OVHcloud]]''
+* 10:30-11:00, Gaëtan Cassiers ([https://www.iaik.tugraz.at/ TU Graz]), ''[[Physical security for cryptographic implementations with open hardware]]''
+* 11:00-11:30, Pat Deegan ([https://psychogenic.com Psychogenic Technologies]), ''[[Black-tie Python: Formal verification with Amaranth]]''
+* 11:30-12:00, Pablo Navarro ([http://www.imse-cnm.csic.es/home.php Seville Institute of Microelectronics]), ''[[Exploring open hardware solutions for ensuring the security of RISC-V processors]]''
+* '''12:00-13:30''', '''lunch break'''
+* 13:30-14:00, Gabriel Gouvine ([http://lip6.fr/ LIP6]), ''[[A Yosys plugin for logic locking]]''
+* 14:00-14:30, Wei Cheng, Sylvain Guilley, and Olivier Rioul ([https://telecom-paris.fr Telecom Paris] and [https://secure-ic.com Secure IC]), ''[[All you ever wanted to know about side-channel attacks and protections (and a forthcoming book)]]''
+====IP blocks====
+* 14:30-15:00, Manuel Moser, Patrick Fath, and Harald Pretl ([https://iic.jku.at/ Johannes Kepler University Linz]), ''[[Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology]]''
+====Transistor modelling and circuit simulation====
+* 15:00-15:30, Felix Salfelder ([https://savannah.gnu.org/git/?group=gnucap GnuCap]), ''[[Verilog-AMS in Gnucap]]''
+====Sustainability (part 2)====
+* 15:30-16:00, Maxime Pelcat ([https://www.ietr.fr/maxime-pelcat Univ Rennes, INSA Rennes and IETR]), ''[[Environmental impacts of electronics and the role of open source hardware]]''
+* '''16:00-16:30''', '''Afternoon break.''' Coffee is served on-campus
+* 16:30-17:00, Andrea Quilici ([https://resilio-solutions.com/amael.parreaux-ey Resilio]), ''[[How to foster GreenIT through open hardware?]]''
+* 17:00-17:30, Julia Hess ([https://www.stiftung-nv.de/en/person/julia-hess Stiftung Neue Verantwortung]),  ''[[The importance of EU Academia in developing the chips of the future]]''
+* 17:30-18:00, Maurits Fennis ([https://unbinare.be/ Unbinare]), [[E-Waste Reverse Engineering Toolkit (RET)]]
+====Funding opportunities====
+* 18:00-18:30, Michiel Leenaars ([https://nlnet.nl/ NLnet Foundation]), ''[[An overview of libre silicon and OSHW related efforts within NGI and NLnet]]''
+====Back-end design tools====
+* 18:30-19:00, Osama Hammad Abdel Reheem ([https://www.aucegypt.edu/ The American university in Cairo]), ''[[OpenROAD]]''
+===July 12, Wednesday (Day 3)===
+* 8:30-9:30, Early bird coffee and tea
+====Back-end design tools====
+* 9:30-10:00, Dan Fritchman (UC Berkeley), ''[[Open (and Closed) Source Analog Design with Hdl21 & VLSIR]]''
+* 10:00-10:30, Christophe Alexandre ([https://github.com/xtofalex/naja Naja]), ''[[Naja: project updates and netlist splitting tool]]''
+* 10:30-11:00, Pavel Smirnov ([https://www.meetiqm.com/ IQM]), ''[[KQCircuits – open-source EDA software for designing chips with super conducting qubits]]''
+* 11:00-11:30, Jean-Paul Chaput ([https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 LIP6, Sorbonne Université]), ''[[Coriolis a RTL to GDSII FOSS Design Flow]]''
+* 11:30-12:00, Matthias Köfferlein ([https://www.klayout.de/ KLayout]), ''[[Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks]]''
+* '''12:00-13:30''', '''lunch break'''
+====Teaching and education====
+* 13:30-14:00, Martin Schoeberl ([https://www.imm.dtu.dk/~masca/ DTU Compute]), ''[[Teaching Chip Design with Open-Source Tools]]''
+* 14:00-14:30, Gabriel Doriath Döhler and Constantin Gierczak-Galle ([https://www.ens.psl.eu/ École normale supérieure]), ''[[Learning hardware design in the video game Minecraft]]''
+* 14:30-15:00, Johan Euphrosine (Google), ''[[Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks]]''
+==== Paving the road for open source flow: gaps, challenges, opportunities ====
+* 15:00-15:30, [https://peertube.f-si.org/videos/watch/087a7e62-c067-473d-957c-57fd9ce85245 ''open discussion'']
+* 15:30-16:00, conclusions
+== Practical information ==
+*[[FSiC2023 venue|Venue, map, hotels]]
+*[[Guidelines for invited speakers]]
+*[[Mediawiki template for invited speakers]]
 == Donations ==
 We are looking for sponsors to cover extra services at the conference, such as food and beverages. In case of interest, please write at fsic2023 'at' f-si.org.
-==Academic Sponsors==
+==Sponsors==
 [[File:SUS_LIP6_CNRSnew.jpg|500px|link=https://www.lip6.fr]]
 [[File:irill.png|300px|link=https://www.irill.org]]
+[[File:RedCatDevices.jpg|200px|link=https://redcatdevices.eu/]]
+[[File:Nitrokey.svg|300px|link=https://www.nitrokey.com]]
 ==Acknowledgements==

Difference between revisions of "FSiC2023"

Latest revision as of 17:08, 1 October 2023

Contents

News

Objectives and motto

Submission

Participation

Organizing committee

Conference program

July 10, Monday (Day 1)

Welcome

Keynote speech

High-level design and logic-synthesis

Foundries and PDKs

On-going FOS silicon projects

Sustainability (part 1)

July 11, Tuesday (Day 2)

Keynote speech

Hardware security

IP blocks

Transistor modelling and circuit simulation

Sustainability (part 2)

Funding opportunities

Back-end design tools

July 12, Wednesday (Day 3)

Back-end design tools

Teaching and education

Paving the road for open source flow: gaps, challenges, opportunities

Practical information

Donations

Sponsors

Acknowledgements

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