Short pages

Showing below up to 50 results in range #101 to #150.

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101. (hist) ‎Software-Defined Hardware: Digital Design in the 21st Century with Chisel ‎[1,463 bytes]
102. (hist) ‎Black-tie Python: Formal verification with Amaranth ‎[1,472 bytes]
103. (hist) ‎Caravel Panamax: The Next Generation ‎[1,480 bytes]
104. (hist) ‎Recent Developments from YosysHQ ‎[1,505 bytes]
105. (hist) ‎CACE: Defining an open-source analog and mixed-signal design flow ‎[1,522 bytes]
106. (hist) ‎Mixing software abstractions for high-level FPGA programming ‎[1,540 bytes]
107. (hist) ‎Standard-cell recognition ‎[1,543 bytes]
108. (hist) ‎Beyond tape-out: open the dark side ‎[1,557 bytes]
109. (hist) ‎TestPageX ‎[1,585 bytes]
110. (hist) ‎Teaching Chip Design with Open-Source Tools ‎[1,610 bytes]
111. (hist) ‎ACM2 – A design-oriented model for open-source tools ‎[1,614 bytes]
112. (hist) ‎The ACT EDA flow for asynchronous logic ‎[1,672 bytes]
113. (hist) ‎OpenEPDA: photonic PDKs with open standards ‎[1,720 bytes]
114. (hist) ‎Tutorial and FAQ on physical verification, DRC+LVS ‎[1,728 bytes]
115. (hist) ‎Generating DRC Runsets for IHP's OpenPDK - Lessons Learned ‎[1,732 bytes]
116. (hist) ‎Toward a collaborative environment for Open Hardware Design ‎[1,735 bytes]
117. (hist) ‎Integrating Mixed-Signal Microelectronics and Photonics: A Co-Design Approach with Piel ‎[1,755 bytes]
118. (hist) ‎Project Arrakeen: a PDKMaster based framework for scalable and portable digital and analog circuits ‎[1,763 bytes]
119. (hist) ‎OpenRAM: An Open-Source Memory Compiler ‎[1,792 bytes]
120. (hist) ‎Converting 45nm transistor netlists to open standards ‎[1,798 bytes]
121. (hist) ‎Open source Design Flow status and roadmap for IHP BiCMOS technology ‎[1,823 bytes]
122. (hist) ‎The Raven chip: First-time silicon success with qflow and efabless ‎[1,824 bytes]
123. (hist) ‎65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview ‎[1,835 bytes]
124. (hist) ‎E-Waste Reverse Engineering Toolkit (RET) ‎[1,844 bytes]
125. (hist) ‎The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies ‎[1,854 bytes]
126. (hist) ‎Environmental impacts of electronics and the role of open source hardware ‎[1,879 bytes]
127. (hist) ‎Free Silicon Foundation (I) ETS ‎[1,892 bytes]
128. (hist) ‎Unlocking the power: energy management open-source analog building blocks from concept to silicon-proven IP ‎[1,894 bytes]
129. (hist) ‎Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana ‎[1,950 bytes]
130. (hist) ‎FSiC2019 venue ‎[1,982 bytes]
131. (hist) ‎German Microelectronics Design Initiative ‎[1,989 bytes]
132. (hist) ‎Verilog-A Circuit Analysis Kernel (VACASK) ‎[2,000 bytes]
133. (hist) ‎Open-Source Verification of Digital ASIC/FPGA Circuits ‎[2,027 bytes]
134. (hist) ‎Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes ‎[2,043 bytes]
135. (hist) ‎Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ‎[2,058 bytes]
136. (hist) ‎Open Documentation Standards and Open Toolchains ‎[2,109 bytes]
137. (hist) ‎Inclusive Modeling with SysMD ‎[2,143 bytes]
138. (hist) ‎KQCircuits – open-source EDA software for designing chips with super conducting qubits ‎[2,158 bytes]
139. (hist) ‎Proof-of-concept for scalable analog blocks using the PDKMaster framework ‎[2,164 bytes]
140. (hist) ‎Horizon 2021 Coordination and Support Action (CSA) proposal ‎[2,186 bytes]
141. (hist) ‎Guidelines for speakers ‎[2,218 bytes]
142. (hist) ‎Coriolis (installation) ‎[2,232 bytes]
143. (hist) ‎Achieving Competitive Performance with Open EDA Tools on a 2MGE Open-Source Linux-Capable RISC-V SoC ‎[2,295 bytes]
144. (hist) ‎KLayout XSection tool - Deep insights or nonsense in colors? ‎[2,351 bytes]
145. (hist) ‎Degate: The stakes and challenges of silicon reverse engineering ‎[2,394 bytes]
146. (hist) ‎Verilog-AMS in Gnucap (2024) ‎[2,437 bytes]
147. (hist) ‎The development of the NSXLIB standard cell scalable library ‎[2,529 bytes]
148. (hist) ‎Hands-on with KLayout: Design rule checks and layout to netlist tools ‎[2,540 bytes]
149. (hist) ‎Open-source electronic design automation for agile network defense at OVHcloud ‎[2,555 bytes]
150. (hist) ‎Tender for GPL-compatible hardware licence development ‎[2,575 bytes]

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