Short pages

Showing below up to 50 results in range #1 to #50.

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1. (hist) ‎CERN Open Hardware License (OHL) ‎[25 bytes]
2. (hist) ‎LIP6 Welcome ‎[105 bytes]
3. (hist) ‎CIAN Team Welcome ‎[107 bytes]
4. (hist) ‎Analyzing open-source chip design ecosystem from an environmental sustainability perspective ‎[153 bytes]
5. (hist) ‎LiteX: an open-source SoC builder and library based on Migen Python DSL ‎[178 bytes]
6. (hist) ‎Digital placement algorithms in Coriolis ‎[218 bytes]
7. (hist) ‎Standard Cell Library report ‎[238 bytes]
8. (hist) ‎Challenge to Fabricate LSI without NDA with Open Method ‎[244 bytes]
9. (hist) ‎Towards digital sovereignty by open source (hardware) ‎[258 bytes]
10. (hist) ‎Gdsfactory ‎[267 bytes]
11. (hist) ‎F-Si Donations ‎[273 bytes]
12. (hist) ‎Introduction to the GoIT project ‎[292 bytes]
13. (hist) ‎Main Page/Software ‎[307 bytes]
14. (hist) ‎Welcome from LIP6 ‎[333 bytes]
15. (hist) ‎Ngspice - an open source mixed signal circuit simulator ‎[403 bytes]
16. (hist) ‎FSiC2020 ‎[405 bytes]
17. (hist) ‎Welcome from the Free Silicon Foundation 2023 ‎[417 bytes]
18. (hist) ‎GnuCap: Progress and Opportunities ‎[428 bytes]
19. (hist) ‎An overview of libre silicon and OSHW related efforts within NGI and NLnet ‎[439 bytes]
20. (hist) ‎FSiC2019 reimbursement ‎[471 bytes]
21. (hist) ‎Synthesis with ghdl ‎[492 bytes]
22. (hist) ‎Libre Silicon Compiler ‎[552 bytes]
23. (hist) ‎Placement algorithms for standard cells in Coriolis ‎[559 bytes]
24. (hist) ‎How to foster GreenIT through open hardware? ‎[595 bytes]
25. (hist) ‎LibrEDA ‎[598 bytes]
26. (hist) ‎The open-source and low-cost echo-stethoscope project ‎[616 bytes]
27. (hist) ‎Coriolis a RTL to GDSII FOSS Design Flow ‎[639 bytes]
28. (hist) ‎From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD ‎[649 bytes]
29. (hist) ‎GAUT ‎[664 bytes]
30. (hist) ‎Coriolis (tutorials) ‎[668 bytes]
31. (hist) ‎The Alliance/Coriolis design flow ‎[672 bytes]
32. (hist) ‎ASICone. Goals, timeline, participants and tools ‎[722 bytes]
33. (hist) ‎Naja: project updates and netlist splitting tool ‎[760 bytes]
34. (hist) ‎Open Source in Healthcare, an hardware approach: the echOpen project case ‎[772 bytes]
35. (hist) ‎OpenSource PDK - A key enabler to unlock the potential of an open source design flow ‎[772 bytes]
36. (hist) ‎Toward multi-language open-source HDL simulation ‎[779 bytes]
37. (hist) ‎Gnu Circuit Analysis Package (GnuCap) ‎[785 bytes]
38. (hist) ‎Free Silicon Foundation ‎[787 bytes]
39. (hist) ‎Main Page ‎[789 bytes]
40. (hist) ‎CMOS functional abstraction ‎[811 bytes]
41. (hist) ‎LibrEDA - digital place-and-route framework from scratch ‎[819 bytes]
42. (hist) ‎FSiC2021 ‎[825 bytes]
43. (hist) ‎OpenROAD ‎[826 bytes]
44. (hist) ‎LibreCell ‎[831 bytes]
45. (hist) ‎Wishbone: a free SoC bus family ‎[840 bytes]
46. (hist) ‎Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology ‎[840 bytes]
47. (hist) ‎Open (and Closed) Source Analog Design with Hdl21 & VLSIR ‎[847 bytes]
48. (hist) ‎Learning hardware design in the video game Minecraft ‎[873 bytes]
49. (hist) ‎A Yosys plugin for logic locking ‎[901 bytes]
50. (hist) ‎Wiki/openic ‎[902 bytes]

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