Pages without language links

Showing below up to 44 results in range #101 to #144.

View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)

101. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries
102. Physical security for cryptographic implementations with open hardware
103. Placement algorithms for standard cells in Coriolis
104. Porting software to hardware using XLS and open source PDKs
105. Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites
106. Proof-of-concept for scalable analog blocks using the PDKMaster framework
107. Recent Developments from YosysHQ
108. Recommendations and roadmap for the development of open-source silicon in the EU
109. Recommendations for the EC on how to reduce the environmental impact of the ICT sector
110. Revolutionize your chip design with GDSFactory and Open Source PDKs
111. Software-Defined Hardware: Digital Design in the 21st Century with Chisel
112. Standard-cell characterization
113. Standard-cell recognition
114. Standard-cell synthesis
115. Standard Cell Library report
116. Statute of the Free Silicon Foundation (I) ETS
117. Synthesis with ghdl
118. SystemC AMS and upcoming free frameworks for the free design
119. Teaching Chip Design with Open-Source Tools
120. TestPageX
121. The ACT EDA flow for asynchronous logic
122. The Alliance/Coriolis design flow
123. The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies
124. The Raven chip: First-time silicon success with qflow and efabless
125. The development of the NSXLIB standard cell scalable library
126. The importance of EU Academia in developing the chips of the future
127. The open-source and low-cost echo-stethoscope project
128. The road to fully open hardware mobile computing
129. TinyTapeout - what happened and next steps
130. Toward a collaborative environment for Open Hardware Design
131. Toward multi-language open-source HDL simulation
132. Towards digital sovereignty by open source (hardware)
133. Tutorial and FAQ on physical verification, DRC+LVS
134. VACASK: a Verilog-A Circuit Analysis Kernel
135. Verilog-AMS in Gnucap
136. Verilog-AMS in Gnucap (2024)
137. Verilog-A Circuit Analysis Kernel (VACASK)
138. Welcome from LIP6
139. Welcome from the Free Silicon Foundation 2023
140. White paper for the EC, January 2020
141. Whom do you trust?: Validating process parameters for open-source tools
142. Wiki/openic
143. Wishbone: a free SoC bus family
144. XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design

View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)