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Showing below up to 50 results in range #101 to #150.
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- LibrEDA - digital place-and-route framework from scratch (6 revisions)
- PyOpus - a Python library for design automation (6 revisions)
- KQCircuits – open-source EDA software for designing chips with super conducting qubits (7 revisions)
- Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology (7 revisions)
- Toward a collaborative environment for Open Hardware Design (7 revisions)
- Coriolis (installation) (7 revisions)
- Gnu Circuit Analysis Package (GnuCap) (7 revisions)
- TinyTapeout - what happened and next steps (7 revisions)
- Challenge to Fabricate LSI without NDA with Open Method (7 revisions)
- Verilog-A Circuit Analysis Kernel (VACASK) (7 revisions)
- FSiC2021 (7 revisions)
- Merging Gnucap and Qucs -- The Why and How (8 revisions)
- Wiki/openic (8 revisions)
- KLayout XSection tool - Deep insights or nonsense in colors? (8 revisions)
- Need for a free alternative to OpenAccess (by Matthias) (8 revisions)
- Environmental impacts of electronics and the role of open source hardware (8 revisions)
- The development of the NSXLIB standard cell scalable library (8 revisions)
- Mixed-signal system modelling and simulation (8 revisions)
- Standard-cell synthesis (8 revisions)
- FSiC2023 venue (8 revisions)
- Software-Defined Hardware: Digital Design in the 21st Century with Chisel (9 revisions)
- Open Source Parasitic Extraction (9 revisions)
- LibreCell (9 revisions)
- Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana (10 revisions)
- Mixing software abstractions for high-level FPGA programming (10 revisions)
- FSiC2019 venue (10 revisions)
- Teaching Chip Design with Open-Source Tools (10 revisions)
- From filters to CMOS transistors - A library of analog schematics with automated sizing (12 revisions)
- VACASK: a Verilog-A Circuit Analysis Kernel (12 revisions)
- KLayout's deep verification base project (13 revisions)
- Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry? (13 revisions)
- Hands-on with KLayout: Design rule checks and layout to netlist tools (13 revisions)
- Inclusive Modeling with SysMD (13 revisions)
- Horizon 2021 Coordination and Support Action (CSA) proposal (14 revisions)
- SystemC AMS and upcoming free frameworks for the free design (15 revisions)
- OpenRAM: An Open-Source Memory Compiler (15 revisions)
- FSiC2020 (18 revisions)
- FOS standard cell generator from scratch (18 revisions)
- Standard-cell characterization (19 revisions)
- CMP add on services - Towards Foundry PDKs on Free CAD Tools (23 revisions)
- High level system modelling, hands-on computer session (23 revisions)
- 65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview (23 revisions)
- FSiC2024 (24 revisions)
- Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes (25 revisions)
- Guidelines for speakers (27 revisions)
- FSiC2022 venue (29 revisions)
- Main Page (32 revisions)
- FSiC2023 (57 revisions)
- FSiC2022 (92 revisions)
- FSiC2019 (111 revisions)