Long pages

Showing below up to 50 results in range #101 to #150.

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101. (hist) ‎Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites ‎[1,271 bytes]
102. (hist) ‎From Theory to Tape-Out: Chip Design Education with Edu4Chip ‎[1,244 bytes]
103. (hist) ‎Working towards FOSS RF IC design in SKY130 ‎[1,231 bytes]
104. (hist) ‎Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks ‎[1,225 bytes]
105. (hist) ‎Verilog-AMS in Gnucap ‎[1,222 bytes]
106. (hist) ‎ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals ‎[1,221 bytes]
107. (hist) ‎XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design ‎[1,205 bytes]
108. (hist) ‎F8 ‎[1,193 bytes]
109. (hist) ‎Composing an out-of-order CPU using software technics ‎[1,190 bytes]
110. (hist) ‎Accessibility and availability of Open EDA tools: the nightmare of distributions’ dependencies ‎[1,188 bytes]
111. (hist) ‎GHDL and the economy of EDA FOSS ‎[1,185 bytes]
112. (hist) ‎Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks ‎[1,183 bytes]
113. (hist) ‎Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon ‎[1,166 bytes]
114. (hist) ‎Moving toward VexiiRiscv ‎[1,163 bytes]
115. (hist) ‎How many designs can you fit on a single die ‎[1,148 bytes]
116. (hist) ‎Fault, Open-Source EDA's Missing DFT Toolchain ‎[1,137 bytes]
117. (hist) ‎FOSS EKV3 Charge-based MOS Transistor Model: an Engineering and Educational Tool ‎[1,104 bytes]
118. (hist) ‎Naja edit: An Open Source Tool for Gate-Level Netlist Optimization and Editing ‎[1,090 bytes]
119. (hist) ‎Mixed-signal system modelling and simulation ‎[1,030 bytes]
120. (hist) ‎The road to fully open hardware mobile computing ‎[1,005 bytes]
121. (hist) ‎A progressive introduction to memory bus interconnect API in Software-Defined Hardware ‎[971 bytes]
122. (hist) ‎TinyTapeout - what happened and next steps ‎[967 bytes]
123. (hist) ‎How to debug a simulation? ‎[964 bytes]
124. (hist) ‎GAUT - A Free and Open-Source High-Level Synthesis tool ‎[959 bytes]
125. (hist) ‎CERN OHL v2 draft ‎[954 bytes]
126. (hist) ‎IHP open source PDK: KLayout Pycell Development status ‎[936 bytes]
127. (hist) ‎Wiki/openic ‎[902 bytes]
128. (hist) ‎A Yosys plugin for logic locking ‎[901 bytes]
129. (hist) ‎Learning hardware design in the video game Minecraft ‎[873 bytes]
130. (hist) ‎It's nice to have a choice: using Haskell for circuit design ‎[855 bytes]
131. (hist) ‎Open (and Closed) Source Analog Design with Hdl21 & VLSIR ‎[847 bytes]
132. (hist) ‎Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology ‎[840 bytes]
133. (hist) ‎Wishbone: a free SoC bus family ‎[840 bytes]
134. (hist) ‎Liberty74: An Open-Source Verilog-to-PCB Flow ‎[834 bytes]
135. (hist) ‎LibreCell ‎[831 bytes]
136. (hist) ‎OpenROAD ‎[826 bytes]
137. (hist) ‎FSiC2021 ‎[825 bytes]
138. (hist) ‎LibrEDA - digital place-and-route framework from scratch ‎[819 bytes]
139. (hist) ‎CMOS functional abstraction ‎[811 bytes]
140. (hist) ‎Main Page ‎[805 bytes]
141. (hist) ‎Free Silicon Foundation ‎[802 bytes]
142. (hist) ‎Gnu Circuit Analysis Package (GnuCap) ‎[785 bytes]
143. (hist) ‎Toward multi-language open-source HDL simulation ‎[779 bytes]
144. (hist) ‎OpenSource PDK - A key enabler to unlock the potential of an open source design flow ‎[772 bytes]
145. (hist) ‎Open Source in Healthcare, an hardware approach: the echOpen project case ‎[772 bytes]
146. (hist) ‎Naja: project updates and netlist splitting tool ‎[760 bytes]
147. (hist) ‎Circuit design with Open EDA tools: a case study ‎[756 bytes]
148. (hist) ‎Moosic: Writing a Yosys Plugin for Design for Trust ‎[753 bytes]
149. (hist) ‎ASICone. Goals, timeline, participants and tools ‎[722 bytes]
150. (hist) ‎The long tail of semiconductors - Education, Tools and Artisanal ASICs ‎[712 bytes]

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