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Showing below up to 39 results in range #101 to #139.

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101. Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites
102. Proof-of-concept for scalable analog blocks using the PDKMaster framework
103. Recent Developments from YosysHQ
104. Recommendations and roadmap for the development of open-source silicon in the EU
105. Recommendations for the EC on how to reduce the environmental impact of the ICT sector
106. Revolutionize your chip design with GDSFactory and Open Source PDKs
107. Software-Defined Hardware: Digital Design in the 21st Century with Chisel
108. Standard-cell characterization
109. Standard-cell recognition
110. Standard-cell synthesis
111. Standard Cell Library report
112. Statute of the Free Silicon Foundation (I) ETS
113. Synthesis with ghdl
114. SystemC AMS and upcoming free frameworks for the free design
115. Teaching Chip Design with Open-Source Tools
116. TestPageX
117. The ACT EDA flow for asynchronous logic
118. The Alliance/Coriolis design flow
119. The Raven chip: First-time silicon success with qflow and efabless
120. The development of the NSXLIB standard cell scalable library
121. The importance of EU Academia in developing the chips of the future
122. The open-source and low-cost echo-stethoscope project
123. The road to fully open hardware mobile computing
124. TinyTapeout - what happened and next steps
125. Toward a collaborative environment for Open Hardware Design
126. Toward multi-language open-source HDL simulation
127. Towards digital sovereignty by open source (hardware)
128. Tutorial and FAQ on physical verification, DRC+LVS
129. VACASK: a Verilog-A Circuit Analysis Kernel
130. Verilog-AMS in Gnucap
131. Verilog-AMS in Gnucap (2024)
132. Verilog-A Circuit Analysis Kernel (VACASK)
133. Welcome from LIP6
134. Welcome from the Free Silicon Foundation 2023
135. White paper for the EC, January 2020
136. Whom do you trust?: Validating process parameters for open-source tools
137. Wiki/openic
138. Wishbone: a free SoC bus family
139. XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design

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