Pages with the most revisions

Showing below up to 50 results in range #31 to #80.

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31. KLayout XSection tool - Deep insights or nonsense in colors?‏‎ (8 revisions)
32. Need for a free alternative to OpenAccess (by Matthias)‏‎ (8 revisions)
33. Environmental impacts of electronics and the role of open source hardware‏‎ (8 revisions)
34. The development of the NSXLIB standard cell scalable library‏‎ (8 revisions)
35. Mixed-signal system modelling and simulation‏‎ (8 revisions)
36. Standard-cell synthesis‏‎ (8 revisions)
37. FSiC2023 venue‏‎ (8 revisions)
38. Merging Gnucap and Qucs -- The Why and How‏‎ (8 revisions)
39. Wiki/openic‏‎ (8 revisions)
40. Gnu Circuit Analysis Package (GnuCap)‏‎ (7 revisions)
41. TinyTapeout - what happened and next steps‏‎ (7 revisions)
42. Challenge to Fabricate LSI without NDA with Open Method‏‎ (7 revisions)
43. FSiC2021‏‎ (7 revisions)
44. Verilog-A Circuit Analysis Kernel (VACASK)‏‎ (7 revisions)
45. Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology‏‎ (7 revisions)
46. KQCircuits – open-source EDA software for designing chips with super conducting qubits‏‎ (7 revisions)
47. Toward a collaborative environment for Open Hardware Design‏‎ (7 revisions)
48. Coriolis (installation)‏‎ (7 revisions)
49. GAUT - A Free and Open-Source High-Level Synthesis tool‏‎ (6 revisions)
50. Black-tie Python: Formal verification with Amaranth‏‎ (6 revisions)
51. LibrEDA - digital place-and-route framework from scratch‏‎ (6 revisions)
52. PyOpus - a Python library for design automation‏‎ (6 revisions)
53. Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks‏‎ (6 revisions)
54. The Alliance/Coriolis design flow‏‎ (6 revisions)
55. GHDL and the economy of EDA FOSS‏‎ (6 revisions)
56. F8‏‎ (6 revisions)
57. ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals‏‎ (6 revisions)
58. The importance of EU Academia in developing the chips of the future‏‎ (6 revisions)
59. The Raven chip: First-time silicon success with qflow and efabless‏‎ (5 revisions)
60. Digital placement algorithms in Coriolis‏‎ (5 revisions)
61. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks‏‎ (5 revisions)
62. Towards digital sovereignty by open source (hardware)‏‎ (5 revisions)
63. Whom do you trust?: Validating process parameters for open-source tools‏‎ (5 revisions)
64. F-Si Donations‏‎ (5 revisions)
65. Standard-cell recognition‏‎ (5 revisions)
66. OpenROAD‏‎ (5 revisions)
67. From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD‏‎ (5 revisions)
68. FSiC2024 venue‏‎ (5 revisions)
69. Welcome from LIP6‏‎ (5 revisions)
70. Exploring open hardware solutions for ensuring the security of RISC-V processors‏‎ (5 revisions)
71. Tutorial and FAQ on physical verification, DRC+LVS‏‎ (5 revisions)
72. Proof-of-concept for scalable analog blocks using the PDKMaster framework‏‎ (5 revisions)
73. Learning hardware design in the video game Minecraft‏‎ (5 revisions)
74. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries‏‎ (5 revisions)
75. A Yosys plugin for logic locking‏‎ (5 revisions)
76. CERN OHL v2 draft‏‎ (5 revisions)
77. Open source Design Flow status and roadmap for IHP BiCMOS technology‏‎ (5 revisions)
78. White paper for the EC, January 2020‏‎ (5 revisions)
79. Toward multi-language open-source HDL simulation‏‎ (4 revisions)
80. Verilog-AMS in Gnucap‏‎ (4 revisions)

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