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Showing below up to 49 results in range #101 to #149.
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- (hist) The Raven chip: First-time silicon success with qflow and efabless [1,824 bytes]
- (hist) 65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview [1,835 bytes]
- (hist) E-Waste Reverse Engineering Toolkit (RET) [1,844 bytes]
- (hist) Environmental impacts of electronics and the role of open source hardware [1,879 bytes]
- (hist) Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana [1,950 bytes]
- (hist) FSiC2019 venue [1,982 bytes]
- (hist) Verilog-A Circuit Analysis Kernel (VACASK) [2,000 bytes]
- (hist) Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes [2,043 bytes]
- (hist) Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design [2,058 bytes]
- (hist) Inclusive Modeling with SysMD [2,143 bytes]
- (hist) KQCircuits – open-source EDA software for designing chips with super conducting qubits [2,158 bytes]
- (hist) Proof-of-concept for scalable analog blocks using the PDKMaster framework [2,164 bytes]
- (hist) Horizon 2021 Coordination and Support Action (CSA) proposal [2,186 bytes]
- (hist) Guidelines for speakers [2,218 bytes]
- (hist) Coriolis (installation) [2,232 bytes]
- (hist) Degate: The stakes and challenges of silicon reverse engineering [2,280 bytes]
- (hist) Verilog-AMS in Gnucap (2024) [2,317 bytes]
- (hist) KLayout XSection tool - Deep insights or nonsense in colors? [2,351 bytes]
- (hist) VACASK: a Verilog-A Circuit Analysis Kernel [2,356 bytes]
- (hist) The development of the NSXLIB standard cell scalable library [2,529 bytes]
- (hist) Hands-on with KLayout: Design rule checks and layout to netlist tools [2,540 bytes]
- (hist) Open-source electronic design automation for agile network defense at OVHcloud [2,555 bytes]
- (hist) FSiC2024 venue [2,576 bytes]
- (hist) FSiC2023 venue [2,632 bytes]
- (hist) FOS standard cell generator from scratch [2,671 bytes]
- (hist) CMP add on services - Towards Foundry PDKs on Free CAD Tools [2,913 bytes]
- (hist) High level Simulation [2,916 bytes]
- (hist) SystemC AMS and upcoming free frameworks for the free design [2,967 bytes]
- (hist) Merging Gnucap and Qucs -- The Why and How [3,157 bytes]
- (hist) Matthias:UnsortedThroughsOnFOSSForEDA [3,355 bytes]
- (hist) The importance of EU Academia in developing the chips of the future [3,552 bytes]
- (hist) Physical security for cryptographic implementations with open hardware [3,822 bytes]
- (hist) From filters to CMOS transistors - A library of analog schematics with automated sizing [3,892 bytes]
- (hist) Need for a free alternative to OpenAccess (by Matthias) [3,970 bytes]
- (hist) FSiC2022 venue [4,571 bytes]
- (hist) Recommendations and roadmap for the development of open-source silicon in the EU [5,411 bytes]
- (hist) Standard-cell synthesis [6,553 bytes]
- (hist) F-Si Statute [6,568 bytes]
- (hist) Recommendations for the EC on how to reduce the environmental impact of the ICT sector [7,632 bytes]
- (hist) Open Source Parasitic Extraction [8,445 bytes]
- (hist) FSiC2019 [11,221 bytes]
- (hist) KiCad [11,255 bytes]
- (hist) FSiC2022 [13,360 bytes]
- (hist) FSiC2023 [13,400 bytes]
- (hist) FSiC2024 [13,758 bytes]
- (hist) Standard-cell characterization [16,183 bytes]
- (hist) White paper for the EC, January 2020 [20,934 bytes]
- (hist) High level system modelling, hands-on computer session [24,004 bytes]
- (hist) Statute of the Free Silicon Foundation (I) ETS [35,187 bytes]