Long pages

Showing below up to 50 results in range #1 to #50.

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1. (hist) ‎Statute of the Free Silicon Foundation (I) ETS ‎[35,187 bytes]
2. (hist) ‎High level system modelling, hands-on computer session ‎[24,004 bytes]
3. (hist) ‎White paper for the EC, January 2020 ‎[20,934 bytes]
4. (hist) ‎Standard-cell characterization ‎[16,282 bytes]
5. (hist) ‎FSiC2024 ‎[16,259 bytes]
6. (hist) ‎FSiC2023 ‎[13,400 bytes]
7. (hist) ‎FSiC2022 ‎[13,360 bytes]
8. (hist) ‎FSiC2025 draft 193841 ‎[11,467 bytes]
9. (hist) ‎FSiC2025 ‎[11,363 bytes]
10. (hist) ‎KiCad ‎[11,255 bytes]
11. (hist) ‎FSiC2019 ‎[11,221 bytes]
12. (hist) ‎Open Source Parasitic Extraction ‎[8,445 bytes]
13. (hist) ‎Recommendations for the EC on how to reduce the environmental impact of the ICT sector ‎[7,632 bytes]
14. (hist) ‎F-Si Statute ‎[6,687 bytes]
15. (hist) ‎Standard-cell synthesis ‎[6,553 bytes]
16. (hist) ‎Recommendations and roadmap for the development of open-source silicon in the EU ‎[5,411 bytes]
17. (hist) ‎FSiC2022 venue ‎[4,571 bytes]
18. (hist) ‎2024-Talk-MichielLeenaars ‎[4,194 bytes]
19. (hist) ‎Need for a free alternative to OpenAccess (by Matthias) ‎[3,970 bytes]
20. (hist) ‎From filters to CMOS transistors - A library of analog schematics with automated sizing ‎[3,892 bytes]
21. (hist) ‎Physical security for cryptographic implementations with open hardware ‎[3,822 bytes]
22. (hist) ‎The European Union must keep funding free software open letter ‎[3,740 bytes]
23. (hist) ‎The importance of EU Academia in developing the chips of the future ‎[3,552 bytes]
24. (hist) ‎Matthias:UnsortedThroughsOnFOSSForEDA ‎[3,355 bytes]
25. (hist) ‎Tight side-channel security bounds on hardware cryptographic engines ‎[3,165 bytes]
26. (hist) ‎Merging Gnucap and Qucs -- The Why and How ‎[3,157 bytes]
27. (hist) ‎SystemC AMS and upcoming free frameworks for the free design ‎[2,967 bytes]
28. (hist) ‎PyOpus - a Python library for design automation ‎[2,950 bytes]
29. (hist) ‎High level Simulation ‎[2,916 bytes]
30. (hist) ‎CMP add on services - Towards Foundry PDKs on Free CAD Tools ‎[2,913 bytes]
31. (hist) ‎FSiC2024 venue ‎[2,736 bytes]
32. (hist) ‎FOS standard cell generator from scratch ‎[2,671 bytes]
33. (hist) ‎FSiC2023 venue ‎[2,632 bytes]
34. (hist) ‎VACASK: a Verilog-A Circuit Analysis Kernel ‎[2,629 bytes]
35. (hist) ‎OpenROAD and The OpenROAD Initiative: Foundations for Open Innovation ‎[2,580 bytes]
36. (hist) ‎Tender for GPL-compatible hardware licence development ‎[2,575 bytes]
37. (hist) ‎Open-source electronic design automation for agile network defense at OVHcloud ‎[2,555 bytes]
38. (hist) ‎Hands-on with KLayout: Design rule checks and layout to netlist tools ‎[2,540 bytes]
39. (hist) ‎The development of the NSXLIB standard cell scalable library ‎[2,529 bytes]
40. (hist) ‎Verilog-AMS in Gnucap (2024) ‎[2,437 bytes]
41. (hist) ‎Degate: The stakes and challenges of silicon reverse engineering ‎[2,394 bytes]
42. (hist) ‎KLayout XSection tool - Deep insights or nonsense in colors? ‎[2,351 bytes]
43. (hist) ‎Achieving Competitive Performance with Open EDA Tools on a 2MGE Open-Source Linux-Capable RISC-V SoC ‎[2,295 bytes]
44. (hist) ‎Coriolis (installation) ‎[2,232 bytes]
45. (hist) ‎Guidelines for speakers ‎[2,218 bytes]
46. (hist) ‎Horizon 2021 Coordination and Support Action (CSA) proposal ‎[2,186 bytes]
47. (hist) ‎Proof-of-concept for scalable analog blocks using the PDKMaster framework ‎[2,164 bytes]
48. (hist) ‎KQCircuits – open-source EDA software for designing chips with super conducting qubits ‎[2,158 bytes]
49. (hist) ‎Inclusive Modeling with SysMD ‎[2,143 bytes]
50. (hist) ‎Open Documentation Standards and Open Toolchains ‎[2,109 bytes]

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