Short pages

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Showing below up to 35 results in range #151 to #185.

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  1. (hist) ‎OpenROAD and The OpenROAD Initiative: Foundations for Open Innovation ‎[2,580 bytes]
  2. (hist) ‎VACASK: a Verilog-A Circuit Analysis Kernel ‎[2,629 bytes]
  3. (hist) ‎FSiC2023 venue ‎[2,632 bytes]
  4. (hist) ‎FOS standard cell generator from scratch ‎[2,671 bytes]
  5. (hist) ‎FSiC2024 venue ‎[2,736 bytes]
  6. (hist) ‎CMP add on services - Towards Foundry PDKs on Free CAD Tools ‎[2,913 bytes]
  7. (hist) ‎High level Simulation ‎[2,916 bytes]
  8. (hist) ‎PyOpus - a Python library for design automation ‎[2,950 bytes]
  9. (hist) ‎SystemC AMS and upcoming free frameworks for the free design ‎[2,967 bytes]
  10. (hist) ‎Merging Gnucap and Qucs -- The Why and How ‎[3,157 bytes]
  11. (hist) ‎Tight side-channel security bounds on hardware cryptographic engines ‎[3,165 bytes]
  12. (hist) ‎Matthias:UnsortedThroughsOnFOSSForEDA ‎[3,355 bytes]
  13. (hist) ‎The importance of EU Academia in developing the chips of the future ‎[3,552 bytes]
  14. (hist) ‎The European Union must keep funding free software open letter ‎[3,740 bytes]
  15. (hist) ‎Physical security for cryptographic implementations with open hardware ‎[3,822 bytes]
  16. (hist) ‎From filters to CMOS transistors - A library of analog schematics with automated sizing ‎[3,892 bytes]
  17. (hist) ‎Need for a free alternative to OpenAccess (by Matthias) ‎[3,970 bytes]
  18. (hist) ‎2024-Talk-MichielLeenaars ‎[4,194 bytes]
  19. (hist) ‎FSiC2022 venue ‎[4,571 bytes]
  20. (hist) ‎Recommendations and roadmap for the development of open-source silicon in the EU ‎[5,411 bytes]
  21. (hist) ‎Standard-cell synthesis ‎[6,553 bytes]
  22. (hist) ‎F-Si Statute ‎[6,687 bytes]
  23. (hist) ‎Recommendations for the EC on how to reduce the environmental impact of the ICT sector ‎[7,632 bytes]
  24. (hist) ‎Open Source Parasitic Extraction ‎[8,445 bytes]
  25. (hist) ‎FSiC2019 ‎[11,221 bytes]
  26. (hist) ‎KiCad ‎[11,255 bytes]
  27. (hist) ‎FSiC2022 ‎[13,360 bytes]
  28. (hist) ‎FSiC2023 ‎[13,400 bytes]
  29. (hist) ‎FSiC2025 ‎[13,648 bytes]
  30. (hist) ‎FSiC2025 draft 193841 ‎[13,648 bytes]
  31. (hist) ‎FSiC2024 ‎[16,259 bytes]
  32. (hist) ‎Standard-cell characterization ‎[16,282 bytes]
  33. (hist) ‎White paper for the EC, January 2020 ‎[20,934 bytes]
  34. (hist) ‎High level system modelling, hands-on computer session ‎[24,004 bytes]
  35. (hist) ‎Statute of the Free Silicon Foundation (I) ETS ‎[35,187 bytes]

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