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Showing below up to 30 results in range #121 to #150.
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- Standard Cell Library report
- Statute of the Free Silicon Foundation (I) ETS
- Synthesis with ghdl
- SystemC AMS and upcoming free frameworks for the free design
- Teaching Chip Design with Open-Source Tools
- TestPageX
- The ACT EDA flow for asynchronous logic
- The Alliance/Coriolis design flow
- The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies
- The Raven chip: First-time silicon success with qflow and efabless
- The development of the NSXLIB standard cell scalable library
- The importance of EU Academia in developing the chips of the future
- The open-source and low-cost echo-stethoscope project
- The road to fully open hardware mobile computing
- TinyTapeout - what happened and next steps
- Toward a collaborative environment for Open Hardware Design
- Toward multi-language open-source HDL simulation
- Towards digital sovereignty by open source (hardware)
- Tutorial and FAQ on physical verification, DRC+LVS
- VACASK: a Verilog-A Circuit Analysis Kernel
- Verilog-AMS in Gnucap
- Verilog-AMS in Gnucap (2024)
- Verilog-A Circuit Analysis Kernel (VACASK)
- Welcome from LIP6
- Welcome from the Free Silicon Foundation 2023
- White paper for the EC, January 2020
- Whom do you trust?: Validating process parameters for open-source tools
- Wiki/openic
- Wishbone: a free SoC bus family
- XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design