Difference between revisions of "FSiC2019"

Free Silicon Conference 2019
Genre	Free software and free hardware development conference
Location(s)	Paris, Sorbonne Université
Country	France
Website	wiki.f-si.org/index.php/FSiC2019

Latest revision as of 17:09, 1 October 2023

The second Free Silicon Conference (FSiC) took place at Sorbonne Université (Paris) on March 14-16 2019. The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification. The conference consisted of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion continued until late in an informal and relaxed atmosphere at the on-campus caves Esclangon.

All video recordings are available on peertube.

Video recordings, slides and documentation

All the talks have been recorded and can be watched on peertube. Extra documentation and the slides of most talks can be found by clicking on the respective titles in the program below.

Participation

Attendance to the conference was free of charge. Lunches, dinners and drinks were offered by Sorbonne Université, LIP6 laboratory. However, due to the limited number of spaces available, seats had to be reserved before February *21* by writing at fsic2019 'at' f-si.org.

The submission window closed on January 31 2019.

Organizing committee

Marie-Minerve Louërat, LIP6, CNRS
Roselyne Chotin, LIP6, Sorbonne Université
Jean-Paul Chaput, LIP6, Sorbonne Université
Luca Alloatti, ETH-Zurich
Matthias Koefferlein, KLayout project
Sean Cross, Kosagi
Thomas Kramer, ETH-Zurich

Conference program

March 14, Thursday (Day 1)

Registration

9:00-9:30, Registration and coffee

Welcome

9:35-9:45, LIP6 Director Fabrice Kordon LIP6 Welcome
9:45-9:50, CIAN team within LIP6 CIAN Team Welcome
9:50-9:55, Welcome from the Free Silicon Foundation

Evening program "beer & baguette" on-campus

19:00-22:00: drinks are served
19:30: dinner is served
21:00: end of the day

March 15, Friday (Day 2)

Morning Coffee

8:30-9:00, Early bird coffee and tea

Impact of FOS hardware

9:00-9:30, Olivier de Fresnoye, Open Source in Healthcare, an hardware approach: the echOpen project case, echopen
9:30-10:00, Edmund Humenberger, ASICone. Goals, timeline, participants and tools, Symbiotic EDA
10:00-10:30, Staf Verhaegen, Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon, Chips4Makers

Foundries, PDKs and cell libraries

10:30-11:00, Jean-Christophe Crébier, Kholdoun Torki, CMP add on services - Towards Foundry PDKs on Free CAD Tools, CMP
11:00-11:30, Kirti Bhanushali, Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes, NCSU, FreePDK
11:30-12:00, Thomas Benz, Converting 45nm transistor netlists to open standards, ETH Zurich
12:00-12:30, Naohiko Shimizu, The development of the NSXLIB standard cell scalable library, Tokai University
12:30-13:30, lunch is served at the on-campus Le Patio
13:30-14:00, Hagen Sankowski, Popcorn - or how many cells your Standard Cell Library has?, LibreSilicon
14:00-14:30, Matthew Guthaus, OpenRAM: An Open-Source Memory Compiler, OpenRAM, UCSC
14:30-15:00, Thomas Kramer, FOS standard cell generator from scratch, ETH Zurich

Back-end flow and algorithms

15:00-15:30, Gabriel Gouvine, Placement algorithms for standard cells in Coriolis, Local Solver
15:30-16:00, Matthias Köfferlein, KLayout's deep verification base project, KLayout
16:00-16:30, Afternoon break. Coffee is served at the on-campus Le Patio
16:30-17:00, Pirouz Bazargan Sabet, Functional abstraction, Sorbonne Université and LIP6 Laboratory
17:00-17:30, Enrico Di Lorenzo, Open Source parasitic extraction - solutions, challenges, and business models, FastFieldSolvers
17:30-18:00, Tim Edwards, The Raven chip: First-time silicon success with qflow and efabless, Open Circuit Design, Qflow
18:00-18:30, Hagen Sankowski, Somebody is using the Advanced Library Format (ALF)? We like to do!, LibreSilicon

Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)

18:30-21:00: drinks are served
19:30: dinner is served
21:00: end of the day

March 16, Saturday (Day 3)

Morning Coffee

8:30-9:00, Early bird coffee and tea

Licenses

9:00-9:30, Tristan Gingold, CERN OHL v2 draft, CERN

High-level digital design (session II)

9:30-10:00, Guillaume Delbergue, Toward a collaborative environment for Open Hardware Design, Hiventive
10:00-11:00, Frédéric Pétrot, High level system modelling, hands-on computer session, GreenSocs, (Tutorial)

Analog back-end design

11:00-11:30, Marie-Minerve Louërat, From filters to CMOS transistors - A library of analog schematics with automated sizing, LIP6
11:30-12:00, Abhaya Chandra Kammara, ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals, TU Kaiserslautern
12:00-12:30, discussions
12:30-13:30, lunch is served at the on-campus Le Patio

Back-end design

13:30-14:30, Jean-Paul Chaput, The Alliance/Coriolis design flow, LIP6, (Tutorial)
14:30-15:45, Matthias Köfferlein, Hands-on with KLayout: Design rule checks and layout to netlist tools, KLayout, (Tutorial)
15:45-16:00, conclusions

@@ Line 1: / Line 1: @@
-The [https://www-soc.lip6.fr/events/pastevents/2018/ second] '''Free Silicon Conference (FSiC)''' will be held at [https://www-soc.lip6.fr/evenements/ Sorbonne Université] (Paris) on '''March 14-16 2019'''. The conference will bring together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere.
+{{Infobox recurring event
+|name              = Free Silicon Conference 2019
+|logo              = fsic2019_logo.svg
+|genre             = Free software and free hardware development conference
+|location          = Paris, Sorbonne Université
+|country           = France
+|website           = [https://wiki.f-si.org/index.php/FSiC2019 wiki.f-si.org/index.php/FSiC2019]
+}}
+The [https://www-soc.lip6.fr/events/pastevents/2018/ second] '''Free Silicon Conference (FSiC)''' took place at [https://www-soc.lip6.fr/evenements/ Sorbonne Université] (Paris) on '''March 14-16 2019'''. The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification. The conference consisted of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion continued until late in an informal and relaxed atmosphere at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon''].
-== Abstract submission ==
+All '''video recordings''' are available on [https://peertube.f-si.org/video-channels/fsic2019 peertube].
-Everybody is welcome to propose a talk by writing to fsic2019 'at' f-si.org. The submission window opened on December 12 2018 and will close on January 31 2019. Acceptance will be communicated by February 10.
+== Video recordings, slides and documentation ==
+All the talks have been recorded and can be watched on [https://peertube.f-si.org/video-channels/fsic2019 peertube]. Extra documentation and the slides of most talks can be found by clicking on the respective titles in the program below.
 == Participation ==
-Attending the conference is free of charge. However, due to the limited number of spaces available, places must be reserved before February 15 by writing at fsic2019 'at' f-si.org.
+Attendance to the conference was free of charge. Lunches, dinners and drinks were offered by Sorbonne Université, LIP6 laboratory. However, due to the limited number of spaces available, seats had to be reserved before February *21* by writing at fsic2019 'at' f-si.org.
+The submission window closed on January 31 2019.
 == Organizing committee ==
-* Marie-Minerve Louërat, lip6, CNRS
+* Marie-Minerve Louërat, LIP6, CNRS
-* Roselyne Chotin-Avot, lip6, Sorbonne University
+* Roselyne Chotin, LIP6, Sorbonne Université
-* Jean-Paul Chaput, lip6, Sorbonne University
+* Jean-Paul Chaput, LIP6, Sorbonne Université
 * Luca Alloatti, ETH-Zurich
 * Matthias Koefferlein, KLayout project
 * Sean Cross, Kosagi
+* Thomas Kramer, ETH-Zurich
-== Confirmed invited talks ==
+==Conference program==
-The speakers below have ''confirmed'' their attendance. Speakers who gave a tentative agreement are not yet included.
-'''Day 1'''
+=== March 14, Thursday (Day 1) ===
-* [https://puri.sm/about/team/ Todd Weaver], ''Title to be announced'', [https://puri.sm Purism]
+==== Registration ====
-* [http://www.echopen.org/ echopen], The open-source and low-cost echo-stethoscope project
+* 9:00-9:30, Registration and coffee
-* [http://wiring.org.co/about.html Hernando Barragán], Wiring and visions, [http://wiring.org.co/ Wiring]
-* Philippe Coussy, [http://www.gaut.fr/ GAUT], [http://www-labsticc.univ-ubs.fr/~coussy/ Lab-STICC Université Bretagne Sud]
-* Tristan Gingold, ''Title to be announced'',[http://ghdl.free.fr/ GHDL]
-* Frédéric Pétrot, ''High level Simulation'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
-* Pirouz Bazargan Sabet, ''Functional abstraction'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P87 Sorbonne Université and LIP6 Laboratory],
-* Charles Papon, ''From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD'', [https://github.com/SpinalHDL SpinalHDL]
-* Jean Bruant, ''State of the art on high-level hardware description languages to generate VHDL or SystemVerilog'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]
-* Telecom ParisTech, ''Simulation and formal verification at system level'', [https://ttool.telecom-paristech.fr/ TTool]
-* [https://www.uni-due.de/person/1998 Holger Vogt], ''[http://ngspice.sourceforge.net/ ngspice] - an open source mixed signal circuit simulator'',  [http://www.uni-due.de/ebs University Duisburg-Essen]
-* [http://www.mos-ak.org/wg.html Wladek Grabinski], ''MOS-AK FOSS TCAD/EDA Perspective'', [http://mos-ak.org/ MOS-AK (EU)]
-'''Day 2'''
-* Jean-Christophe Crébier, ''CMP add on services'', [https://mycmp.fr/ CMP]
-* Speaker to be announced, ''FreePDK'', [https://www.eda.ncsu.edu/wiki/FreePDK FreePDK]
-* Speaker to be announced, ''LibreSilicon'', [http://libresilicon.com/ LibreSilicon]
-* Thomas Benz, ''Converting 45nm transistor netlists to open standards'', [https://www.ethz.ch ETH Zurich]
-* Naohiko Shimizu, ''The development of the NSXLIB standard cell scalable library'', [http://labo.nshimizu.com/ Tokai University]
-* Thomas Kramer, ''FOS standard cell generator from scratch'', [https://www.ethz.ch ETH Zurich]
-* Matthias Köfferlein, Mask layout database and (new) verification algorithms, [https://klayout.de KLayout]
-* Liliana Andrade, ''Mixed-signal system modelling and simulation'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
-* Gabriel Gouvine, ''Title to be announced'', [https://www.localsolver.com/ Local Solver]
-* Enrico Di Lorenzo, ''Parasitic extraction'', [http://www.fastfieldsolvers.com FastFieldSolvers]
-* Tim Edwards, ''Title to be announced'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]
-'''Day 3'''
+==== Welcome ====
-* Speaker to be announced, ''High level system modelling, hands-on computer session'', [https://www.greensocs.com/about-us GreenSocs]
+* 9:35-9:45, [https://www.lip6.fr/presentation/directeur.php?LANG=en LIP6] Director [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P182 Fabrice Kordon] ''[[LIP6 Welcome]]''
-* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], ''The [https://www-soc.lip6.fr/equipe-cian/logiciels/alliance/ Alliance]/[https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/ Coriolis] design flow'', [https://www.lip6.fr/?LANG=en LIP6]
+* 9:45-9:50, [https://www-soc.lip6.fr/en/team-cian/ CIAN team] within LIP6 ''[[CIAN Team Welcome]]''
-* Matthias Köfferlein, Hands-on with KLayout: Design rule checks and layout to netlist tools, [https://klayout.de KLayout]
+* 9:50-9:55, Welcome from the Free Silicon Foundation
-== Preliminary Program ==
+==== Introduction and motivation for Free and Open Source (FOS) silicon ====
-=== March 14, Thursday (Day 1) ===
+* 10:00-10:30, [https://puri.sm/about/team/ Todd Weaver], ''[https://peertube.f-si.org/videos/watch/d8dcaf9e-88c7-44cf-9f97-d7d96d1d9b28 The Future of Computing and Why You Should Care]'', [https://puri.sm Purism]
-==== Introduction ====
+* 10:30-11:00, [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain]
-* Motivations for Free and Open Source (FOS) hardware
-* Impact on society, academia, makers, industry
-* Impact on cybersecurity
-* Politics and marketing
-* Business opportunities
-==== High-level system requirements ====
+====High-level digital design (session I)====
-* Case studies from the perspective successful Open Hardware projects
+* 11:00-11:30, [http://www-labsticc.univ-ubs.fr/~coussy/ Philippe Coussy], ''[[GAUT - A Free and Open-Source High-Level Synthesis tool]]'', [http://www.gaut.fr/ GAUT], Lab-STICC Université Bretagne Sud
+* 11:30-12:00, Tristan Gingold, ''[[GHDL and the economy of EDA FOSS]]'', [http://ghdl.free.fr/ GHDL]
+* 12:00-12:30, Frédéric Pétrot, ''[[High level Simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]<br><br>
+* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
+* 13:30-14:00, Daniela Genius, ''[[Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P96 Sorbonne Université, LIP6]
+* 14:00-14:30, Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL]
+* 14:30-15:00, Jean Bruant, ''[https://peertube.f-si.org/videos/watch/d36f3f63-fad0-4334-b7b9-82f4be9c89ef State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]
+* 15:00-15:30, Florent Kermarrec, ''[[LiteX: an open-source SoC builder and library based on Migen Python DSL]]'', [http://enjoy-digital.fr/ Enjoy Digital]
-==== High-level digital design (architectural and pre-layout) ====
+====Mixed-signal/analog design and transistor modelling====
-* Architectural opportunities for FOS Hardware
+* 15:30-16:00, Christoph Grimm, ''[[SystemC AMS and upcoming free frameworks for the free design]]'', [https://cps.cs.uni-kl.de/en/staff/christoph-grimm-prof-dr/ Kaiserslautern University]<br><br>
-* High-level hardware description languages to generate VHDL or SystemVerilog
+* '''16:00-16:30''', '''Afternoon break.''' Coffee is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
-* Formal verification
+* 16:30-17:00, Liliana Andrade, ''[[Mixed-signal system modelling and simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
-* High-level virtual prototyping
+* 17:00-17:30, [https://www.uni-due.de/person/1998 Holger Vogt], ''[[ngspice - an open source mixed signal circuit simulator]]'', [http://ngspice.sourceforge.net/ ngspice], [http://www.uni-due.de/ebs University Duisburg-Essen]
+* 17:30-18:00, Al Davis, ''[[Gnu Circuit Analysis Package (GnuCap)]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
+* 18:00-18:30, Felix Salfelder, ''[[GnuCap: Progress and Opportunities]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
-==== Analog design and simulation ====
+====Evening program "beer & baguette" on-campus====
-* Comparison of FOS tools: Coriolis, qucs, KiCad.
+* 19:00-22:00: drinks are served
-* Ngspice
+* 19:30: dinner is served
-* SystemC-AMS
+* 21:00: end of the day
 === March 15, Friday (Day 2) ===
-==== Foundries ====
+==== Morning Coffee ====
-* FOS hardware from the foundry's perspective: legal challenges and opportunities
+* 8:30-9:00, Early bird coffee and tea
-* MakeLSI
+==== Impact of FOS hardware ====
+* 9:00-9:30, Olivier de Fresnoye, ''[[Open Source in Healthcare, an hardware approach: the echOpen project case]]'', [http://www.echopen.org/ echopen]
+* 9:30-10:00, Edmund Humenberger, ''[[ASICone. Goals, timeline, participants and tools]]'', [https://www.symbioticeda.com Symbiotic EDA]
+* 10:00-10:30, Staf Verhaegen, ''[[Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon]]'', [https://www.chips4makers.io/blog Chips4Makers]
-==== Setting up the ingredients ====
+====Foundries, PDKs and cell libraries====
-* Importing PDKs into FOS formats
+* 10:30-11:00, Jean-Christophe Crébier, Kholdoun Torki, ''[[CMP add on services - Towards Foundry PDKs on Free CAD Tools]]'', [https://mycmp.fr/ CMP]
-* Standard cell: generators and modelling
+* 11:00-11:30, Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK]
-* Parametrized analog devices and topologies
+* 11:30-12:00, Thomas Benz, ''[[Converting 45nm transistor netlists to open standards]]'', [https://www.ethz.ch ETH Zurich]
-* Parametrized Optical devices
+* 12:00-12:30, Naohiko Shimizu, ''[[The development of the NSXLIB standard cell scalable library]]'', [http://labo.nshimizu.com/ Tokai University]<br><br>
-* Memory generators
+* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
+* 13:30-14:00, Hagen Sankowski, ''[https://peertube.f-si.org/videos/watch/2bcbad29-2d87-4d1f-b193-ff9317dbc439 Popcorn - or how many cells your Standard Cell Library has?]'', [http://libresilicon.com/ LibreSilicon]
+* 14:00-14:30, [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM: An Open-Source Memory Compiler]]'', [https://vlsida.github.io/OpenRAM/ OpenRAM], UCSC
+* 14:30-15:00, Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]
-==== CAD internals and algorithms - how the tools work ====
+====Back-end flow and algorithms====
-* The role of databases
+* 15:00-15:30, Gabriel Gouvine, ''[[Placement algorithms for standard cells in Coriolis]]'', [https://www.localsolver.com/ Local Solver]
-* Place algorithms
+* 15:30-16:00, Matthias Köfferlein, ''[[KLayout's deep verification base project]]'', [https://klayout.de KLayout]<br><br>
-* Routing algorithms, global and detailed
+* '''16:00-16:30''', '''Afternoon break.''' Coffee is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
-* Timing analysis
+* 16:30-17:00, Pirouz Bazargan Sabet, ''[[Functional abstraction]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P87 Sorbonne Université and LIP6 Laboratory]
-* Power analysis
+* 17:00-17:30, Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers]
-* Formal VHDL verification
+* 17:30-18:00, Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]
+* 18:00-18:30, Hagen Sankowski, ''[https://peertube.f-si.org/videos/watch/6b322173-010b-425e-a98f-dde0b628c989 Somebody is using the Advanced Library Format (ALF)? We like to do!]'', [http://libresilicon.com/ LibreSilicon]
-==== Legal issues ====
+====Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)====
-* The constrains of typical NDAs
+* 18:30-21:00: drinks are served
-* Hardware FOS licenses. State-of-the-art
+* 19:30: dinner is served
+* 21:00: end of the day
 === March 16, Saturday (Day 3) ===
-==== CAD tool usage - demos ====
+==== Morning Coffee ====
-* Synthesis
+* 8:30-9:00, Early bird coffee and tea
-* Place and route tools
-* Timing analysis
-* Clock distribution
-==== Post place-and-route (P&R) verification and simulators ====
+====Licenses====
-* Design Rule Check
+* 9:00-9:30, Tristan Gingold, ''[[CERN OHL v2 draft]]'', [https://www.ohwr.org/project/cernohl/wikis/CERN-OHL-v2-draft CERN]
-* LVS
-* Static Timing Analysis
-* Fault modelling and Automatic Test Pattern Generators (ATPG)
-==== Workshop ====
+====High-level digital design (session II)====
-Further topics and questions raised during the conference will be discussed in plenary or in individual working groups.
+* 9:30-10:00, Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive]
+* 10:00-11:00, Frédéric Pétrot, ''[[High level system modelling, hands-on computer session]]'', [https://www.greensocs.com/about-us GreenSocs], '''(Tutorial)'''
-== Practical information ==
+====Analog back-end design====
+* 11:00-11:30, Marie-Minerve Louërat, ''[[From filters to CMOS transistors - A library of analog schematics with automated sizing]]'', [https://www-soc.lip6.fr/en/team-cian/ LIP6]
+* 11:30-12:00, Abhaya Chandra Kammara, ''[[ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals]]'', [https://www.eit.uni-kl.de/koenig/gemeinsame_seiten/projects/Research%20Projects.htm TU Kaiserslautern]
+* 12:00-12:30, discussions<br><br>
+* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]
-===Address===
+====Back-end design====
-The conference will take place at:
+* 13:30-14:30, [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], ''[[The Alliance/Coriolis design flow]]'', [https://www-soc.lip6.fr/equipe-cian/logiciels LIP6], '''(Tutorial)'''
-<pre>
+* 14:30-15:45, Matthias Köfferlein, ''[[Hands-on with KLayout: Design rule checks and layout to netlist tools]]'', [https://klayout.de KLayout], '''(Tutorial)'''
-Sorbonne Université - LIP6
+* 15:45-16:00, conclusions
-Campus Pierre et Marie Curie
-Place Jussieu
-Paris, France
-</pre>
-[https://www.openstreetmap.org/search?query=%204%20Place%20Jussieu%2075005%20Paris#map=19/48.84752/2.35405 The campus on OpenStreetMap]
+== Practical information ==
+*[[FSiC2019 venue|Venue, map, hotels]]
-=== How to reach the Sorbonne University ===
+*[[FSiC2019 reimbursement|Trip and hotel reimbursement procedure]]
-Sorbonne Université is located very close to the city centre and is well served by the metro (RER) and by bus. Timetables and maps are available [https://www.ratp.fr/en here].
+*[[Guidelines for invited speakers]]
+*[[Mediawiki template for invited speakers]]
-The metro station '''Jussieu''' is just a few steps away from the main entrance and is served by the metro Line 7 and Line 10.
-If arriving by plane to Charles de Gaulle (Roissy), take the metro B until Saint Michel, then take the metro 10 to Jussieu.
-=== Trip and hotel reimbursement procedure ===
-The speakers requesting travel and hotel expenses must send to fsic2019'at'f-si.org the following documents:
-* a quote for the complete expenses by February 15
-* shall this not be possible: an upper boundary to such expenses by February 15
-* bring a copy of the original invoices at the conference
-Based on the expected expenses, the conference organizers will confirm within a week the proposed plan. Only confirmed travel plans will be reimbursed after the conference.
-=== Hotels ===
-There are a number hotels very close to the university, such as:
-* [http://www.hotelroyalcardinal.com/ Hôtel Au Royal Cardinal ]
+==Supporting entities==
-* [https://www.hotelvendomesaintgermain.com/en/ Hôtel Vendome Saint Germain ]
+[[File:SUS_LIP6_CNRSnew.jpg|500px]]
-* [http://www.familiahotel.com/ Familia Hotel]
-* [http://www.parishotelminerve.com/en/ Hôtel Minerve]
-* [http://hotel-cluny.fr/ Hôtel Cluny la Sorbonne]
-* [http://www.familiahotel.com/ Familia Hotel]
-* [https://www.hotel-pierre-nicole.com/fr/galerie-photo.html Hôtel Pierre Nicole]
-* [https://www.accorhotels.com/fr/hotel-3577-ibis-paris-bastille-faubourg-saint-antoine-11eme/index.shtml Hôtel Ibis Bastille]

Difference between revisions of "FSiC2019"

Latest revision as of 17:09, 1 October 2023

Contents

Video recordings, slides and documentation

Participation

Organizing committee

Conference program

March 14, Thursday (Day 1)

Registration

Welcome

Introduction and motivation for Free and Open Source (FOS) silicon

High-level digital design (session I)

Mixed-signal/analog design and transistor modelling

Evening program "beer & baguette" on-campus

March 15, Friday (Day 2)

Morning Coffee

Impact of FOS hardware

Foundries, PDKs and cell libraries

Back-end flow and algorithms

Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)

March 16, Saturday (Day 3)

Morning Coffee

Licenses

High-level digital design (session II)

Analog back-end design

Back-end design

Practical information

Supporting entities

Navigation menu

Search