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|website = [https://wiki.f-si.org/index.php/FSiC2019 wiki.f-si.org/index.php/FSiC2019] | |website = [https://wiki.f-si.org/index.php/FSiC2019 wiki.f-si.org/index.php/FSiC2019] | ||
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The [https://www-soc.lip6.fr/events/pastevents/2018/ second] '''Free Silicon Conference (FSiC)''' | The [https://www-soc.lip6.fr/events/pastevents/2018/ second] '''Free Silicon Conference (FSiC)''' took place at [https://www-soc.lip6.fr/evenements/ Sorbonne Université] (Paris) on '''March 14-16 2019'''. The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification. The conference consisted of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion continued until late in an informal and relaxed atmosphere at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon'']. | ||
All '''video recordings''' are available on [https://peertube.f-si.org/video-channels/fsic2019 peertube]. | |||
== Video recordings, slides and documentation == | |||
All the talks have been recorded and can be watched on [https://peertube.f-si.org/video-channels/fsic2019 peertube]. Extra documentation and the slides of most talks can be found by clicking on the respective titles in the program below. | |||
== Participation == | == Participation == | ||
Attendance to the conference was free of charge. Lunches, dinners and drinks were offered by Sorbonne Université, LIP6 laboratory. However, due to the limited number of spaces available, seats had to be reserved before February *21* by writing at fsic2019 'at' f-si.org. | |||
The submission window closed on January 31 2019. | The submission window closed on January 31 2019. | ||
== Organizing committee == | == Organizing committee == | ||
* Marie-Minerve Louërat, | * Marie-Minerve Louërat, LIP6, CNRS | ||
* Roselyne Chotin, | * Roselyne Chotin, LIP6, Sorbonne Université | ||
* Jean-Paul Chaput, | * Jean-Paul Chaput, LIP6, Sorbonne Université | ||
* Luca Alloatti, ETH-Zurich | * Luca Alloatti, ETH-Zurich | ||
* Matthias Koefferlein, KLayout project | * Matthias Koefferlein, KLayout project | ||
| Line 30: | Line 35: | ||
==== Welcome ==== | ==== Welcome ==== | ||
* 9:35-9:45, [https://www.lip6.fr/presentation/directeur.php?LANG=en LIP6] Director [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P182 Fabrice Kordon] | * 9:35-9:45, [https://www.lip6.fr/presentation/directeur.php?LANG=en LIP6] Director [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P182 Fabrice Kordon] ''[[LIP6 Welcome]]'' | ||
* 9:45-9:50, [https://www-soc.lip6.fr/en/team-cian/ CIAN team] within LIP6 | * 9:45-9:50, [https://www-soc.lip6.fr/en/team-cian/ CIAN team] within LIP6 ''[[CIAN Team Welcome]]'' | ||
* 9:50-9:55, Welcome from the Free Silicon Foundation | * 9:50-9:55, Welcome from the Free Silicon Foundation | ||
==== Introduction and motivation for Free and Open Source (FOS) silicon ==== | ==== Introduction and motivation for Free and Open Source (FOS) silicon ==== | ||
* 10:00-10:30, [https://puri.sm/about/team/ Todd Weaver], '' | * 10:00-10:30, [https://puri.sm/about/team/ Todd Weaver], ''[https://peertube.f-si.org/videos/watch/d8dcaf9e-88c7-44cf-9f97-d7d96d1d9b28 The Future of Computing and Why You Should Care]'', [https://puri.sm Purism] | ||
* 10:30-11:00, [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain] | * 10:30-11:00, [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain] | ||
| Line 45: | Line 50: | ||
* 13:30-14:00, Daniela Genius, ''[[Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P96 Sorbonne Université, LIP6] | * 13:30-14:00, Daniela Genius, ''[[Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P96 Sorbonne Université, LIP6] | ||
* 14:00-14:30, Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL] | * 14:00-14:30, Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL] | ||
* 14:30-15:00, Jean Bruant, ''[ | * 14:30-15:00, Jean Bruant, ''[https://peertube.f-si.org/videos/watch/d36f3f63-fad0-4334-b7b9-82f4be9c89ef State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory] | ||
* 15:00-15:30, Florent Kermarrec, ''[[LiteX: an open-source SoC builder and | * 15:00-15:30, Florent Kermarrec, ''[[LiteX: an open-source SoC builder and library based on Migen Python DSL]]'', [http://enjoy-digital.fr/ Enjoy Digital] | ||
====Mixed-signal/analog design and transistor modelling==== | ====Mixed-signal/analog design and transistor modelling==== | ||
| Line 59: | Line 64: | ||
* 19:00-22:00: drinks are served | * 19:00-22:00: drinks are served | ||
* 19:30: dinner is served | * 19:30: dinner is served | ||
* | * 21:00: end of the day | ||
=== March 15, Friday (Day 2) === | === March 15, Friday (Day 2) === | ||
| Line 68: | Line 73: | ||
* 9:00-9:30, Olivier de Fresnoye, ''[[Open Source in Healthcare, an hardware approach: the echOpen project case]]'', [http://www.echopen.org/ echopen] | * 9:00-9:30, Olivier de Fresnoye, ''[[Open Source in Healthcare, an hardware approach: the echOpen project case]]'', [http://www.echopen.org/ echopen] | ||
* 9:30-10:00, Edmund Humenberger, ''[[ASICone. Goals, timeline, participants and tools]]'', [https://www.symbioticeda.com Symbiotic EDA] | * 9:30-10:00, Edmund Humenberger, ''[[ASICone. Goals, timeline, participants and tools]]'', [https://www.symbioticeda.com Symbiotic EDA] | ||
* 10:00-10:30, Staf Verhaegen, ''[[Lesson learned from Retro-uC and search for ideal | * 10:00-10:30, Staf Verhaegen, ''[[Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon]]'', [https://www.chips4makers.io/blog Chips4Makers] | ||
====Foundries, PDKs and cell libraries==== | ====Foundries, PDKs and cell libraries==== | ||
* 10:30-11:00, Jean-Christophe Crébier, ''[[CMP add on services]]'', [https://mycmp.fr/ CMP] | * 10:30-11:00, Jean-Christophe Crébier, Kholdoun Torki, ''[[CMP add on services - Towards Foundry PDKs on Free CAD Tools]]'', [https://mycmp.fr/ CMP] | ||
* 11:00-11:30, Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK] | * 11:00-11:30, Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK] | ||
* 11:30-12:00, Thomas Benz, ''[[Converting 45nm transistor netlists to open standards]]'', [https://www.ethz.ch ETH Zurich] | * 11:30-12:00, Thomas Benz, ''[[Converting 45nm transistor netlists to open standards]]'', [https://www.ethz.ch ETH Zurich] | ||
* 12:00-12:30, Naohiko Shimizu, ''[[The development of the NSXLIB standard cell scalable library]]'', [http://labo.nshimizu.com/ Tokai University]<br><br> | * 12:00-12:30, Naohiko Shimizu, ''[[The development of the NSXLIB standard cell scalable library]]'', [http://labo.nshimizu.com/ Tokai University]<br><br> | ||
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br> | * '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br> | ||
* 13:30-14:00, Hagen Sankowski, ''[ | * 13:30-14:00, Hagen Sankowski, ''[https://peertube.f-si.org/videos/watch/2bcbad29-2d87-4d1f-b193-ff9317dbc439 Popcorn - or how many cells your Standard Cell Library has?]'', [http://libresilicon.com/ LibreSilicon] | ||
* 14:00-14:30, [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM: An Open-Source Memory Compiler]]'', [https://vlsida.github.io/OpenRAM/ OpenRAM], UCSC | * 14:00-14:30, [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM: An Open-Source Memory Compiler]]'', [https://vlsida.github.io/OpenRAM/ OpenRAM], UCSC | ||
* 14:30-15:00, Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich] | * 14:30-15:00, Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich] | ||
| Line 87: | Line 92: | ||
* 17:00-17:30, Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers] | * 17:00-17:30, Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers] | ||
* 17:30-18:00, Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow] | * 17:30-18:00, Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow] | ||
* 18:00-18:30, | * 18:00-18:30, Hagen Sankowski, ''[https://peertube.f-si.org/videos/watch/6b322173-010b-425e-a98f-dde0b628c989 Somebody is using the Advanced Library Format (ALF)? We like to do!]'', [http://libresilicon.com/ LibreSilicon] | ||
====Evening program "beer & baguette" at the on-campus | ====Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)==== | ||
* | * 18:30-21:00: drinks are served | ||
* 19:30: dinner is served | * 19:30: dinner is served | ||
* | * 21:00: end of the day | ||
=== March 16, Saturday (Day 3) === | === March 16, Saturday (Day 3) === | ||
| Line 104: | Line 108: | ||
====High-level digital design (session II)==== | ====High-level digital design (session II)==== | ||
* 9:30-10:00, Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive] | * 9:30-10:00, Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive] | ||
* 10:00-11:00, | * 10:00-11:00, Frédéric Pétrot, ''[[High level system modelling, hands-on computer session]]'', [https://www.greensocs.com/about-us GreenSocs], '''(Tutorial)''' | ||
====Analog back-end design==== | ====Analog back-end design==== | ||
| Line 124: | Line 128: | ||
==Supporting entities== | ==Supporting entities== | ||
[[File: | [[File:SUS_LIP6_CNRSnew.jpg|500px]] | ||
Latest revision as of 16:09, 1 October 2023
| Free Silicon Conference 2019 | |
|---|---|
 | |
| Genre | Free software and free hardware development conference |
| Location(s) | Paris, Sorbonne Université |
| Country | France |
| Website | wiki.f-si.org/index.php/FSiC2019 |
The second Free Silicon Conference (FSiC) took place at Sorbonne Université (Paris) on March 14-16 2019. The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification. The conference consisted of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion continued until late in an informal and relaxed atmosphere at the on-campus caves Esclangon.
All video recordings are available on peertube.
Video recordings, slides and documentation
All the talks have been recorded and can be watched on peertube. Extra documentation and the slides of most talks can be found by clicking on the respective titles in the program below.
Participation
Attendance to the conference was free of charge. Lunches, dinners and drinks were offered by Sorbonne Université, LIP6 laboratory. However, due to the limited number of spaces available, seats had to be reserved before February *21* by writing at fsic2019 'at' f-si.org.
The submission window closed on January 31 2019.
Organizing committee
- Marie-Minerve Louërat, LIP6, CNRS
- Roselyne Chotin, LIP6, Sorbonne Université
- Jean-Paul Chaput, LIP6, Sorbonne Université
- Luca Alloatti, ETH-Zurich
- Matthias Koefferlein, KLayout project
- Sean Cross, Kosagi
- Thomas Kramer, ETH-Zurich
Conference program
March 14, Thursday (Day 1)
Registration
- 9:00-9:30, Registration and coffee
Welcome
- 9:35-9:45, LIP6 Director Fabrice Kordon LIP6 Welcome
- 9:45-9:50, CIAN team within LIP6 CIAN Team Welcome
- 9:50-9:55, Welcome from the Free Silicon Foundation
Introduction and motivation for Free and Open Source (FOS) silicon
- 10:00-10:30, Todd Weaver, The Future of Computing and Why You Should Care, Purism
- 10:30-11:00, Steffen Reith, Towards digital sovereignty by open source (hardware), Hochschule RheinMain
High-level digital design (session I)
- 11:00-11:30, Philippe Coussy, GAUT - A Free and Open-Source High-Level Synthesis tool, GAUT, Lab-STICC Université Bretagne Sud
- 11:30-12:00, Tristan Gingold, GHDL and the economy of EDA FOSS, GHDL
- 12:00-12:30, Frédéric Pétrot, High level Simulation, Université Grenoble Alpes and TIMA Laboratory
- 12:30-13:30, lunch is served at the on-campus Le Patio
- 13:30-14:00, Daniela Genius, Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design , Sorbonne Université, LIP6
- 14:00-14:30, Charles Papon, From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD, SpinalHDL
- 14:30-15:00, Jean Bruant, State of the art on high-level hardware description languages to generate VHDL or SystemVerilog, OVH and TIMA Laboratory
- 15:00-15:30, Florent Kermarrec, LiteX: an open-source SoC builder and library based on Migen Python DSL, Enjoy Digital
Mixed-signal/analog design and transistor modelling
- 15:30-16:00, Christoph Grimm, SystemC AMS and upcoming free frameworks for the free design, Kaiserslautern University
- 16:00-16:30, Afternoon break. Coffee is served at the on-campus Le Patio
- 16:30-17:00, Liliana Andrade, Mixed-signal system modelling and simulation, Université Grenoble Alpes and TIMA Laboratory
- 17:00-17:30, Holger Vogt, ngspice - an open source mixed signal circuit simulator, ngspice, University Duisburg-Essen
- 17:30-18:00, Al Davis, Gnu Circuit Analysis Package (GnuCap), GnuCap
- 18:00-18:30, Felix Salfelder, GnuCap: Progress and Opportunities, GnuCap
Evening program "beer & baguette" on-campus
- 19:00-22:00: drinks are served
- 19:30: dinner is served
- 21:00: end of the day
March 15, Friday (Day 2)
Morning Coffee
- 8:30-9:00, Early bird coffee and tea
Impact of FOS hardware
- 9:00-9:30, Olivier de Fresnoye, Open Source in Healthcare, an hardware approach: the echOpen project case, echopen
- 9:30-10:00, Edmund Humenberger, ASICone. Goals, timeline, participants and tools, Symbiotic EDA
- 10:00-10:30, Staf Verhaegen, Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon, Chips4Makers
Foundries, PDKs and cell libraries
- 10:30-11:00, Jean-Christophe Crébier, Kholdoun Torki, CMP add on services - Towards Foundry PDKs on Free CAD Tools, CMP
- 11:00-11:30, Kirti Bhanushali, Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes, NCSU, FreePDK
- 11:30-12:00, Thomas Benz, Converting 45nm transistor netlists to open standards, ETH Zurich
- 12:00-12:30, Naohiko Shimizu, The development of the NSXLIB standard cell scalable library, Tokai University
- 12:30-13:30, lunch is served at the on-campus Le Patio
- 13:30-14:00, Hagen Sankowski, Popcorn - or how many cells your Standard Cell Library has?, LibreSilicon
- 14:00-14:30, Matthew Guthaus, OpenRAM: An Open-Source Memory Compiler, OpenRAM, UCSC
- 14:30-15:00, Thomas Kramer, FOS standard cell generator from scratch, ETH Zurich
Back-end flow and algorithms
- 15:00-15:30, Gabriel Gouvine, Placement algorithms for standard cells in Coriolis, Local Solver
- 15:30-16:00, Matthias Köfferlein, KLayout's deep verification base project, KLayout
- 16:00-16:30, Afternoon break. Coffee is served at the on-campus Le Patio
- 16:30-17:00, Pirouz Bazargan Sabet, Functional abstraction, Sorbonne Université and LIP6 Laboratory
- 17:00-17:30, Enrico Di Lorenzo, Open Source parasitic extraction - solutions, challenges, and business models, FastFieldSolvers
- 17:30-18:00, Tim Edwards, The Raven chip: First-time silicon success with qflow and efabless, Open Circuit Design, Qflow
- 18:00-18:30, Hagen Sankowski, Somebody is using the Advanced Library Format (ALF)? We like to do!, LibreSilicon
Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)
- 18:30-21:00: drinks are served
- 19:30: dinner is served
- 21:00: end of the day
March 16, Saturday (Day 3)
Morning Coffee
- 8:30-9:00, Early bird coffee and tea
Licenses
- 9:00-9:30, Tristan Gingold, CERN OHL v2 draft, CERN
High-level digital design (session II)
- 9:30-10:00, Guillaume Delbergue, Toward a collaborative environment for Open Hardware Design, Hiventive
- 10:00-11:00, Frédéric Pétrot, High level system modelling, hands-on computer session, GreenSocs, (Tutorial)
Analog back-end design
- 11:00-11:30, Marie-Minerve Louërat, From filters to CMOS transistors - A library of analog schematics with automated sizing, LIP6
- 11:30-12:00, Abhaya Chandra Kammara, ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals, TU Kaiserslautern
- 12:00-12:30, discussions
- 12:30-13:30, lunch is served at the on-campus Le Patio
Back-end design
- 13:30-14:30, Jean-Paul Chaput, The Alliance/Coriolis design flow, LIP6, (Tutorial)
- 14:30-15:45, Matthias Köfferlein, Hands-on with KLayout: Design rule checks and layout to netlist tools, KLayout, (Tutorial)
- 15:45-16:00, conclusions
Practical information
- Venue, map, hotels
- Trip and hotel reimbursement procedure
- Guidelines for invited speakers
- Mediawiki template for invited speakers
Supporting entities
