Long pages

Showing below up to 20 results in range #31 to #50.

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31. (hist) ‎VACASK: a Verilog-A Circuit Analysis Kernel ‎[2,356 bytes]
32. (hist) ‎KLayout XSection tool - Deep insights or nonsense in colors? ‎[2,351 bytes]
33. (hist) ‎Verilog-AMS in Gnucap (2024) ‎[2,317 bytes]
34. (hist) ‎Degate: The stakes and challenges of silicon reverse engineering ‎[2,280 bytes]
35. (hist) ‎Coriolis (installation) ‎[2,232 bytes]
36. (hist) ‎Guidelines for speakers ‎[2,218 bytes]
37. (hist) ‎Horizon 2021 Coordination and Support Action (CSA) proposal ‎[2,186 bytes]
38. (hist) ‎Proof-of-concept for scalable analog blocks using the PDKMaster framework ‎[2,164 bytes]
39. (hist) ‎KQCircuits – open-source EDA software for designing chips with super conducting qubits ‎[2,158 bytes]
40. (hist) ‎Inclusive Modeling with SysMD ‎[2,143 bytes]
41. (hist) ‎Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ‎[2,058 bytes]
42. (hist) ‎Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes ‎[2,043 bytes]
43. (hist) ‎Verilog-A Circuit Analysis Kernel (VACASK) ‎[2,000 bytes]
44. (hist) ‎FSiC2019 venue ‎[1,982 bytes]
45. (hist) ‎Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana ‎[1,950 bytes]
46. (hist) ‎Environmental impacts of electronics and the role of open source hardware ‎[1,879 bytes]
47. (hist) ‎E-Waste Reverse Engineering Toolkit (RET) ‎[1,844 bytes]
48. (hist) ‎65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview ‎[1,835 bytes]
49. (hist) ‎The Raven chip: First-time silicon success with qflow and efabless ‎[1,824 bytes]
50. (hist) ‎Open source Design Flow status and roadmap for IHP BiCMOS technology ‎[1,823 bytes]

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