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Showing below up to 20 results in range #61 to #80.
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- Wishbone: a free SoC bus family (22:29, 1 August 2022)
- Porting software to hardware using XLS and open source PDKs (22:31, 1 August 2022)
- Synthesis with ghdl (22:32, 1 August 2022)
- How many designs can you fit on a single die (22:33, 1 August 2022)
- Standard Cell Library report (22:34, 1 August 2022)
- Go2async: A high-level synthesis tool for asynchronous circuits (22:36, 1 August 2022)
- KLayout XSection tool - Deep insights or nonsense in colors? (22:37, 1 August 2022)
- OpenSource PDK - A key enabler to unlock the potential of an open source design flow (22:38, 1 August 2022)
- PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries (22:40, 1 August 2022)
- Challenge to Fabricate LSI without NDA with Open Method (22:42, 1 August 2022)
- F8 (22:47, 1 August 2022)
- OpenEPDA: photonic PDKs with open standards (22:56, 1 August 2022)
- Merging Gnucap and Qucs -- The Why and How (22:59, 1 August 2022)
- Whom do you trust?: Validating process parameters for open-source tools (23:00, 1 August 2022)
- LibrEDA - digital place-and-route framework from scratch (23:00, 1 August 2022)
- Digital placement algorithms in Coriolis (23:01, 1 August 2022)
- Naja: an open source framework for EDA post synthesis flow development (23:02, 1 August 2022)
- Tutorial and FAQ on physical verification, DRC+LVS (23:05, 1 August 2022)
- 65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview (11:16, 23 August 2022)
- Wiki/openic (04:02, 4 September 2022)