FSiC2019
| Free Silicon Conference 2019 | |
|---|---|
 | |
| Genre | Free software and free hardware development conference |
| Location(s) | Paris, Sorbonne Université |
| Country | France |
| Website | wiki.f-si.org/index.php/FSiC2019 |
The second Free Silicon Conference (FSiC) will be held at Sorbonne Université (Paris) on March 14-16 2019. The conference will bring together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere at the on-campus caves Esclangon.
Abstract submission
Everybody is welcome to propose a talk by writing to fsic2019 'at' f-si.org. The submission window opened on December 12 2018 and will close on January 31 2019. Acceptance will be communicated by February 10.
Participation
Attending the conference is free of charge. Lunches, dinners and drinks will be offered. However, due to the limited number of spaces available, seats must be reserved before February *21* by writing at fsic2019 'at' f-si.org.
Organizing committee
- Marie-Minerve Louërat, Lip6, CNRS
- Roselyne Chotin, Lip6, Sorbonne Université
- Jean-Paul Chaput, Lip6, Sorbonne Université
- Luca Alloatti, ETH-Zurich
- Matthias Koefferlein, KLayout project
- Sean Cross, Kosagi
- Thomas Kramer, ETH-Zurich
Confirmed invited talks
The speakers below have confirmed their attendance. Speakers who gave a tentative agreement are not yet included.
Day 1
- Todd Weaver, Title to be announced, Purism
- Mehdi Benchoufi, The open-source and low-cost echo-stethoscope project, echopen
- Hernando Barragán, Wiring and visions, Wiring
- Steffen Reith, Towards digital sovereignty by open source (hardware), Hochschule RheinMain
- Edmund Humenberger, ASICone. Goals, timeline, participants and tools, Symbiotic EDA
- Philippe Coussy, GAUT, GAUT, Lab-STICC Université Bretagne Sud
- Tristan Gingold, GHDL and the economy of EDA FOSS, GHDL
- Frédéric Pétrot, High level Simulation, Université Grenoble Alpes and TIMA Laboratory
- Pirouz Bazargan Sabet, Functional abstraction, Sorbonne Université and LIP6 Laboratory
- Charles Papon, From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD, SpinalHDL
- Jean Bruant, State of the art on high-level hardware description languages to generate VHDL or SystemVerilog, OVH and TIMA Laboratory
- Christoph Grimm, SystemC AMS and upcoming free frameworks for the free design, Kaiserslautern University
- Holger Vogt, ngspice - an open source mixed signal circuit simulator, ngspice, University Duisburg-Essen
- Al Davis, Gnu Circuit Analysis Package (GnuCap), GnuCap
- Felix Salfelder, GnuCap: Progress and Opportunities, GnuCap
- Wladek Grabinski, MOS-AK FOSS TCAD/EDA Perspective, MOS-AK (EU)
- Daniela Genius, Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design , Sorbonne Université, LIP6
- Guillaume Delbergue, Toward a collaborative environment for Open Hardware Design, Hiventive
Day 2
- Jean-Christophe Crébier, CMP add on services, CMP
- Kirti Bhanushali, Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes, NCSU, FreePDK
- Thomas Benz, Converting 45nm transistor netlists to open standards, ETH Zurich
- Hagen Sankowski, Popcorn - or how many cells your Standard Cell Library has?, LibreSilicon
- Naohiko Shimizu, The development of the NSXLIB standard cell scalable library, Tokai University
- Matthew Guthaus, OpenRAM, OpenRAM, UCSC
- Thomas Kramer, FOS standard cell generator from scratch, ETH Zurich
- Liliana Andrade, Mixed-signal system modelling and simulation, Université Grenoble Alpes and TIMA Laboratory
- Gabriel Gouvine, Title to be announced, Local Solver
- Matthias Köfferlein, KLayout's deep verification base project, KLayout
- Enrico Di Lorenzo, Open Source parasitic extraction - solutions, challenges, and business models, FastFieldSolvers
- Tim Edwards, The Raven chip: First-time silicon success with qflow and efabless, Open Circuit Design, Qflow
- Andreas Westerwick, Libre Silicon Compiler, LibreSilicon
- Hagen Sankowski, Somebody is using the Advanced Library Format (ALF)? We like to do!, LibreSilicon
Day 3
- Mark Burton, High level system modelling, hands-on computer session, GreenSocs
- Jean-Paul Chaput, The Alliance/Coriolis design flow, LIP6
- Matthias Köfferlein, Hands-on with KLayout: Design rule checks and layout to netlist tools, KLayout
- Abhaya Chandra Kammara, ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals, TU Kaiserslautern
- Marie-Minerve Louërat, From CMOS transistors to filters - A library of analog schematics with automated sizing, LIP6
Preliminary Program
March 14, Thursday (Day 1)
Introduction
- Motivations for Free and Open Source (FOS) hardware
- Impact on society, academia, makers, industry
- Impact on cybersecurity
- Politics and marketing
- Business opportunities
High-level system requirements
- Case studies from the perspective successful Open Hardware projects
High-level digital design (architectural and pre-layout)
- Architectural opportunities for FOS Hardware
- High-level hardware description languages to generate VHDL or SystemVerilog
- Formal verification
- High-level virtual prototyping
Analog design and simulation
- Comparison of FOS tools: Coriolis, qucs, KiCad.
- Ngspice
- SystemC-AMS
March 15, Friday (Day 2)
Foundries
- FOS hardware from the foundry's perspective: legal challenges and opportunities
- MakeLSI
Setting up the ingredients
- Importing PDKs into FOS formats
- Standard cell: generators and modelling
- Parametrized analog devices and topologies
- Parametrized Optical devices
- Memory generators
CAD internals and algorithms - how the tools work
- The role of databases
- Place algorithms
- Routing algorithms, global and detailed
- Timing analysis
- Power analysis
- Formal VHDL verification
Legal issues
- The constrains of typical NDAs
- Hardware FOS licenses. State-of-the-art
March 16, Saturday (Day 3)
CAD tool usage - demos
- Synthesis
- Place and route tools
- Timing analysis
- Clock distribution
Post place-and-route (P&R) verification and simulators
- Design Rule Check
- LVS
- Static Timing Analysis
- Fault modelling and Automatic Test Pattern Generators (ATPG)
Workshop
Further topics and questions raised during the conference will be discussed in plenary or in individual working groups.
Time schedule
Day 1
On the first day the talks begin later for allowing some people to travel in the morning.
- 9:00: registration opens
- 9:30: welcome
- 10:00: first session
- 12:30-13:30: lunch is served at the on-campus Le Patio
- 18:30: end of last session
- 18:30-19:30: break
The evening program "beer & baguette" continues at the on-campus caves Esclangon
- 18:30-23:00: drinks are served
- 19:30: dinner is served
- 23:00: end of the day
Day 2
- 9:00: first session
- 12:30-13:30: lunch is served at the on-campus Le Patio
- 18:30: end of last session
- 18:30-19:30: break
The evening program "beer & baguette" continues at the on-campus caves Esclangon
- 18:30-23:00: drinks are served
- 19:30: dinner is served
- 23:00: end of the day
Day 3
- 9:00: first session
- 12:30-13:30: lunch is served at the on-campus Le Patio
- 16:00: end of last session
Practical information
- Venue, map, hotels
- Trip and hotel reimbursement procedure
- Guidelines for invited speakers
- Mediawiki template for invited speakers
Supporting entities
