Difference between revisions of "FSiC2019"

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The [https://www-soc.lip6.fr/events/pastevents/2018/ second] '''Free Silicon Conference (FSiC)''' will be held at [https://www-soc.lip6.fr/evenements/ Sorbonne Université] (Paris) on '''March 14-16 2019'''. The conference will bring together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon''].
The [https://www-soc.lip6.fr/events/pastevents/2018/ second] '''Free Silicon Conference (FSiC)''' will be held at [https://www-soc.lip6.fr/evenements/ Sorbonne Université] (Paris) on '''March 14-16 2019'''. The conference will bring together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon''].
== Abstract submission ==
Everybody is welcome to propose a talk by writing to fsic2019 'at' f-si.org. The submission window opened on December 12 2018 and will close on January 31 2019. Acceptance will be communicated by February 10.


== Participation ==
== Participation ==
Attending the conference is free of charge. Lunches, dinners and drinks will be offered. However, due to the limited number of spaces available, seats must be reserved before February *21* by writing at fsic2019 'at' f-si.org.
Attending the conference is free of charge. Lunches, dinners and drinks will be offered. However, due to the limited number of spaces available, seats must be reserved before February *21* by writing at fsic2019 'at' f-si.org.
The submission window closed on January 31 2019.


== Organizing committee ==
== Organizing committee ==
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* Thomas Kramer, ETH-Zurich
* Thomas Kramer, ETH-Zurich


== Confirmed invited talks ==
==Conference program==
The speakers below have ''confirmed'' their attendance. Speakers who gave a tentative agreement are not yet included.


'''Day 1'''
=== March 14, Thursday (Day 1) ===
==== Introduction and motivation for Free and Open Source (FOS) silicon ====
* [https://puri.sm/about/team/ Todd Weaver], ''Title to be announced'', [https://puri.sm Purism]
* [https://puri.sm/about/team/ Todd Weaver], ''Title to be announced'', [https://puri.sm Purism]
* Mehdi Benchoufi, ''[[The open-source and low-cost echo-stethoscope project]]'', [http://www.echopen.org/ echopen]
* [http://wiring.org.co/about.html Hernando Barragán], ''[[Wiring and visions]]'', [http://wiring.org.co/ Wiring]
* [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain]
* [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain]
* Edmund Humenberger, ''[[ASICone. Goals, timeline, participants and tools]]'', [https://www.symbioticeda.com Symbiotic EDA]
 
====High-level digital design (session I)====
* [http://www-labsticc.univ-ubs.fr/~coussy/ Philippe Coussy], ''[[GAUT]]'', [http://www.gaut.fr/ GAUT], Lab-STICC Université Bretagne Sud
* [http://www-labsticc.univ-ubs.fr/~coussy/ Philippe Coussy], ''[[GAUT]]'', [http://www.gaut.fr/ GAUT], Lab-STICC Université Bretagne Sud
* Tristan Gingold, ''[[GHDL and the economy of EDA FOSS]]'', [http://ghdl.free.fr/ GHDL]
* Tristan Gingold, ''[[GHDL and the economy of EDA FOSS]]'', [http://ghdl.free.fr/ GHDL]
* Frédéric Pétrot, ''[[High level Simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* Frédéric Pétrot, ''[[High level Simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* Pirouz Bazargan Sabet, ''[[Functional abstraction]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P87 Sorbonne Université and LIP6 Laboratory]
* Daniela Genius, ''[[Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P96 Sorbonne Université, LIP6]
* Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL]
* Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL]
* Jean Bruant, ''[[State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]
* Jean Bruant, ''[[State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]
====Mixed-signal/analog design and transistor modelling====
* Christoph Grimm, ''[[SystemC AMS and upcoming free frameworks for the free design]]'', [https://cps.cs.uni-kl.de/en/staff/christoph-grimm-prof-dr/ Kaiserslautern University]
* Christoph Grimm, ''[[SystemC AMS and upcoming free frameworks for the free design]]'', [https://cps.cs.uni-kl.de/en/staff/christoph-grimm-prof-dr/ Kaiserslautern University]
* Liliana Andrade, ''[[Mixed-signal system modelling and simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* [https://www.uni-due.de/person/1998 Holger Vogt], ''[[ngspice - an open source mixed signal circuit simulator]]'', [http://ngspice.sourceforge.net/ ngspice], [http://www.uni-due.de/ebs University Duisburg-Essen]
* [https://www.uni-due.de/person/1998 Holger Vogt], ''[[ngspice - an open source mixed signal circuit simulator]]'', [http://ngspice.sourceforge.net/ ngspice], [http://www.uni-due.de/ebs University Duisburg-Essen]
* Al Davis, ''[[Gnu Circuit Analysis Package (GnuCap)]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* Al Davis, ''[[Gnu Circuit Analysis Package (GnuCap)]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* Felix Salfelder, ''[[GnuCap: Progress and Opportunities]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* Felix Salfelder, ''[[GnuCap: Progress and Opportunities]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* [http://www.mos-ak.org/wg.html Wladek Grabinski], ''[[MOS-AK FOSS TCAD/EDA Perspective]]'', [http://mos-ak.org/ MOS-AK (EU)]
* [http://www.mos-ak.org/wg.html Wladek Grabinski], ''[[MOS-AK FOSS TCAD/EDA Perspective]]'', [http://mos-ak.org/ MOS-AK (EU)]
* Daniela Genius, ''[[Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P96 Sorbonne Université, LIP6]
* Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive]


'''Day 2'''
=== March 15, Friday (Day 2) ===
==== Impact of FOS hardware ====
* Olivier de Fresnoye, ''[[The open-source and low-cost echo-stethoscope project]]'', [http://www.echopen.org/ echopen]
* Edmund Humenberger, ''[[ASICone. Goals, timeline, participants and tools]]'', [https://www.symbioticeda.com Symbiotic EDA]
 
====Foundries, PDKs and cell libraries====
* Jean-Christophe Crébier, ''[[CMP add on services]]'', [https://mycmp.fr/ CMP]
* Jean-Christophe Crébier, ''[[CMP add on services]]'', [https://mycmp.fr/ CMP]
* Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK]
* Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK]
Line 55: Line 59:
* [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM]]'', [https://openram.soe.ucsc.edu/ OpenRAM, UCSC]
* [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM]]'', [https://openram.soe.ucsc.edu/ OpenRAM, UCSC]
* Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]
* Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]
* Liliana Andrade, ''[[Mixed-signal system modelling and simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
 
====Back-end flow and algorithms====
* Gabriel Gouvine, ''Title to be announced'', [https://www.localsolver.com/ Local Solver]
* Gabriel Gouvine, ''Title to be announced'', [https://www.localsolver.com/ Local Solver]
* Matthias Köfferlein, ''[[KLayout's deep verification base project]]'', [https://klayout.de KLayout]
* Matthias Köfferlein, ''[[KLayout's deep verification base project]]'', [https://klayout.de KLayout]
* Pirouz Bazargan Sabet, ''[[Functional abstraction]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P87 Sorbonne Université and LIP6 Laboratory]
* Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers]
* Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers]
* Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]
* Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]
Line 63: Line 69:
* Hagen Sankowski, ''[[Somebody is using the Advanced Library Format (ALF)? We like to do!]]'', [http://libresilicon.com/ LibreSilicon]
* Hagen Sankowski, ''[[Somebody is using the Advanced Library Format (ALF)? We like to do!]]'', [http://libresilicon.com/ LibreSilicon]


'''Day 3'''
===High-level digital design (session II)===
* Mark Burton, ''[[High level system modelling, hands-on computer session]]'', [https://www.greensocs.com/about-us GreenSocs]
* Florent Kermarrec, ''[[LiteX: an open-source SoC builder and libraty based on Migen Python DSL]]'', [http://enjoy-digital.fr/ Enjoy Digital]
* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], ''[[The Alliance/Coriolis design flow]]'', [https://www-soc.lip6.fr/equipe-cian/logiciels LIP6]
* Matthias Köfferlein, ''[[Hands-on with KLayout: Design rule checks and layout to netlist tools]]'', [https://klayout.de KLayout]
* Abhaya Chandra Kammara, ''[[ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals]]'', [https://www.eit.uni-kl.de/koenig/gemeinsame_seiten/projects/Research%20Projects.htm TU Kaiserslautern]
* Marie-Minerve Louërat, ''[[From CMOS transistors to filters - A library of analog schematics with automated sizing]]'', [https://www-soc.lip6.fr/en/team-cian/ LIP6]
 
== Preliminary Program ==
=== March 14, Thursday (Day 1) ===
==== Introduction ====
* Motivations for Free and Open Source (FOS) hardware
* Impact on society, academia, makers, industry
* Impact on cybersecurity
* Politics and marketing
* Business opportunities
 
==== High-level system requirements ====
* Case studies from the perspective successful Open Hardware projects
 
==== High-level digital design (architectural and pre-layout) ====
* Architectural opportunities for FOS Hardware
* High-level hardware description languages to generate VHDL or SystemVerilog
* Formal verification
* High-level virtual prototyping
 
==== Analog design and simulation ====
* Comparison of FOS tools: Coriolis, qucs, KiCad.
* Ngspice
* SystemC-AMS
 
=== March 15, Friday (Day 2) ===
==== Foundries ====
* FOS hardware from the foundry's perspective: legal challenges and opportunities
* MakeLSI
 
==== Setting up the ingredients ====
* Importing PDKs into FOS formats
* Standard cell: generators and modelling
* Parametrized analog devices and topologies
* Parametrized Optical devices
* Memory generators
 
==== CAD internals and algorithms - how the tools work ====
* The role of databases
* Place algorithms
* Routing algorithms, global and detailed
* Timing analysis
* Power analysis
* Formal VHDL verification
 
==== Legal issues ====
* The constrains of typical NDAs
* Hardware FOS licenses. State-of-the-art


=== March 16, Saturday (Day 3) ===
=== March 16, Saturday (Day 3) ===
==== CAD tool usage - demos ====
====High-level digital design (session III)====
* Synthesis
* Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive]
* Place and route tools
* Mark Burton, ''[[High level system modelling, hands-on computer session]]'', [https://www.greensocs.com/about-us GreenSocs], '''(Tutorial)'''
* Timing analysis
* Clock distribution


==== Post place-and-route (P&R) verification and simulators ====
====Analog back-end design====
* Design Rule Check
* Abhaya Chandra Kammara, ''[[ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals]]'', [https://www.eit.uni-kl.de/koenig/gemeinsame_seiten/projects/Research%20Projects.htm TU Kaiserslautern]
* LVS
* Marie-Minerve Louërat, ''[[From filters to CMOS transistors - A library of analog schematics with automated sizing]]'', [https://www-soc.lip6.fr/en/team-cian/ LIP6]
* Static Timing Analysis
* Fault modelling and Automatic Test Pattern Generators (ATPG)


==== Workshop ====
====Back-end design====
Further topics and questions raised during the conference will be discussed in plenary or in individual working groups.
* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], ''[[The Alliance/Coriolis design flow]]'', [https://www-soc.lip6.fr/equipe-cian/logiciels LIP6], '''(Tutorial)'''
* Matthias Köfferlein, ''[[Hands-on with KLayout: Design rule checks and layout to netlist tools]]'', [https://klayout.de KLayout], '''(Tutorial)'''


== Time schedule ==
== Time schedule ==

Revision as of 13:54, 25 February 2019

Free Silicon Conference 2019
Fsic2019 logo.svg
GenreFree software and free hardware development conference
Location(s)Paris, Sorbonne Université
CountryFrance
Websitewiki.f-si.org/index.php/FSiC2019

The second Free Silicon Conference (FSiC) will be held at Sorbonne Université (Paris) on March 14-16 2019. The conference will bring together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere at the on-campus caves Esclangon.

Participation

Attending the conference is free of charge. Lunches, dinners and drinks will be offered. However, due to the limited number of spaces available, seats must be reserved before February *21* by writing at fsic2019 'at' f-si.org.

The submission window closed on January 31 2019.

Organizing committee

  • Marie-Minerve Louërat, Lip6, CNRS
  • Roselyne Chotin, Lip6, Sorbonne Université
  • Jean-Paul Chaput, Lip6, Sorbonne Université
  • Luca Alloatti, ETH-Zurich
  • Matthias Koefferlein, KLayout project
  • Sean Cross, Kosagi
  • Thomas Kramer, ETH-Zurich

Conference program

March 14, Thursday (Day 1)

Introduction and motivation for Free and Open Source (FOS) silicon

High-level digital design (session I)

Mixed-signal/analog design and transistor modelling

March 15, Friday (Day 2)

Impact of FOS hardware

Foundries, PDKs and cell libraries

Back-end flow and algorithms

High-level digital design (session II)

March 16, Saturday (Day 3)

High-level digital design (session III)

Analog back-end design

Back-end design

Time schedule

Day 1

On the first day the talks begin later for allowing some people to travel in the morning.

  • 9:00: registration opens
  • 9:30: welcome
  • 10:00: first session
  • 12:30-13:30: lunch is served at the on-campus Le Patio
  • 18:30: end of last session
  • 18:30-19:30: break

The evening program "beer & baguette" continues at the on-campus caves Esclangon

  • 18:30-23:00: drinks are served
  • 19:30: dinner is served
  • 23:00: end of the day

Day 2

  • 9:00: first session
  • 12:30-13:30: lunch is served at the on-campus Le Patio
  • 18:30: end of last session
  • 18:30-19:30: break

The evening program "beer & baguette" continues at the on-campus caves Esclangon

  • 18:30-23:00: drinks are served
  • 19:30: dinner is served
  • 23:00: end of the day

Day 3

  • 9:00: first session
  • 12:30-13:30: lunch is served at the on-campus Le Patio
  • 16:00: end of last session

Practical information

Supporting entities

LIP6 SU CNRS logo.jpg

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