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Showing below up to 20 results in range #11 to #30.
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- LIP6 Welcome (19:20, 29 March 2019)
- CIAN Team Welcome (19:23, 29 March 2019)
- GAUT - A Free and Open-Source High-Level Synthesis tool (17:11, 16 July 2019)
- Towards digital sovereignty by open source (hardware) (17:11, 16 July 2019)
- GHDL and the economy of EDA FOSS (17:13, 16 July 2019)
- High level Simulation (17:15, 16 July 2019)
- Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design (17:17, 16 July 2019)
- From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD (17:18, 16 July 2019)
- LiteX: an open-source SoC builder and library based on Migen Python DSL (17:25, 16 July 2019)
- SystemC AMS and upcoming free frameworks for the free design (17:28, 16 July 2019)
- Mixed-signal system modelling and simulation (17:30, 16 July 2019)
- Ngspice - an open source mixed signal circuit simulator (17:34, 16 July 2019)
- Gnu Circuit Analysis Package (GnuCap) (17:35, 16 July 2019)
- GnuCap: Progress and Opportunities (17:36, 16 July 2019)
- Open Source in Healthcare, an hardware approach: the echOpen project case (17:37, 16 July 2019)
- ASICone. Goals, timeline, participants and tools (17:39, 16 July 2019)
- Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon (17:40, 16 July 2019)
- CMP add on services - Towards Foundry PDKs on Free CAD Tools (17:43, 16 July 2019)
- Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes (17:44, 16 July 2019)
- Converting 45nm transistor netlists to open standards (17:45, 16 July 2019)