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- 16:54, 21 March 2019 diff hist +66 Standard-cell characterization Link to Tas/Yagle
- 16:50, 21 March 2019 diff hist +1,571 Standard-cell characterization Dependent setup and hold time
- 16:38, 18 March 2019 diff hist +43 N File:Transistor folding.svg Transistor folding/fingering. current
- 16:38, 18 March 2019 diff hist +1 m Standard-cell synthesis →= Netlist synthesis
- 16:37, 18 March 2019 diff hist +35 Standard-cell synthesis →Background
- 16:36, 18 March 2019 diff hist +272 Standard-cell synthesis →Pin Placement
- 13:25, 18 March 2019 diff hist +22 LibreCell Add link to OHL wikipedia page.
- 13:19, 18 March 2019 diff hist +90 Main Page/Software Add link to LibreCell. current
- 13:15, 18 March 2019 diff hist +47 Standard-cell characterization Add link to LibreCell
- 13:13, 18 March 2019 diff hist +63 LibreCell Add links to layout synthesis and characterization pages.
- 13:10, 18 March 2019 diff hist +116 N File:Dffposx1 setup time plot 1ps sim step.png Propagation delay of a D flip flop as a function of the unconditional setup time (infinite hold time). current
- 13:09, 18 March 2019 diff hist +71 N File:Setup hold types comparision.json.svg Comparison of independent and dependent setup/hold times. current
- 13:07, 18 March 2019 diff hist +46 N File:Dependent hold time measurement.json.svg Dependent hold time measurement. current
- 13:05, 18 March 2019 diff hist +45 N File:Dependent setup time measurement.json.svg Measuring dependent setup time. current
- 13:04, 18 March 2019 diff hist +75 N File:Setup time sweep.svg Measuring unconditional setup time by sweeping the data edge. current
- 13:01, 18 March 2019 diff hist +104 N File:Measuring unconditional setup hold.json.svg Measuring setup and hold constraints by sweeping the data edge relative to the clock edge. current
- 12:59, 18 March 2019 diff hist +69 N File:Xor2x1 wave example.svg Input and output waveforms of a XOR2X1 cell (FreePDK45) current
- 12:58, 18 March 2019 diff hist +43 N File:Freepdk xor2x1 fall delay sweep.png Example of NDLM timing table. current
- 12:57, 18 March 2019 diff hist +10,353 N Standard-cell characterization Created page with "Standard-cell characterization refers to the process of compiling data about the behavior of [https://en.wikipedia.org/wiki/Standard_cell standard-cells]. Just knowing the log..."
- 12:15, 16 March 2019 diff hist +73 ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals →General information: Add link to website.