Difference between revisions of "LibreCell"
Jump to navigation
Jump to search
(Add link to OHL wikipedia page.) |
|||
Line 8: | Line 8: | ||
| genre = Electronic Design Automation (EDA) | | genre = Electronic Design Automation (EDA) | ||
| license = AGPLv3 / [https://en.wikipedia.org/wiki/CERN_Open_Hardware_Licence CERN OHL-S v2] | | license = AGPLv3 / [https://en.wikipedia.org/wiki/CERN_Open_Hardware_Licence CERN OHL-S v2] | ||
| website = https://codeberg.org | | website = https://codeberg.org/librecell | ||
}} | }} | ||
LibreCell is a toolbox for automated CMOS [[Standard-cell synthesis|standard-cell synthesis]]. It's mainly focused on automated layout generation and [[Standard-cell characterization|timing characterization]]. The goal of the project is to generate a full standard-cell library based on abstract descriptions of the cells (e.g. netlists) and design rules of the target technology. | LibreCell is a toolbox for automated CMOS [[Standard-cell synthesis|standard-cell synthesis]]. It's mainly focused on automated layout generation and [[Standard-cell characterization|timing characterization]]. The goal of the project is to generate a full standard-cell library based on abstract descriptions of the cells (e.g. netlists) and design rules of the target technology. |
Revision as of 00:32, 16 December 2022
Original author(s) | Thomas Kramer |
---|---|
Repository | https://codeberg.org/tok/librecell |
Written in | Python |
Operating system | Linux |
Type | Electronic Design Automation (EDA) |
License | AGPLv3 / CERN OHL-S v2 |
Website | https://codeberg.org/librecell |
LibreCell is a toolbox for automated CMOS standard-cell synthesis. It's mainly focused on automated layout generation and timing characterization. The goal of the project is to generate a full standard-cell library based on abstract descriptions of the cells (e.g. netlists) and design rules of the target technology.