Toward multi-language open-source HDL simulation

• Speaker(s): Tristan Gingold
• email: Tristan Gingold

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Abstract

GHDL was first a compiled VHDL simulator. It was later extended to support synthesis, either standalone and generating a simple vhdl or verilog netlist), or as a plugin for yosys. Recently a limited support of verilog has been added in order to improve the support of mixed-language design synthesis. The rules to mix designs are discussed in this presentation.

Software

General information

• Repository: https://github.com/ghdl/ghdl
• Main documentation website: https://github.com/ghdl/ghdl

Roadmap

• The project seeks help on: AMS