Difference between revisions of "Toward multi-language open-source HDL simulation"
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==Downloads== | ==Downloads== | ||
* [[:File:Ghdl-multi-lang-slides.pdf | * [[:File:Ghdl-multi-lang-slides.pdf|slides]] | ||
* [https://peertube.f-si.org/videos/watch/8c735e58-bf3d-4d62-95f9-ff2965979cf3 Video recording] | * [https://peertube.f-si.org/videos/watch/8c735e58-bf3d-4d62-95f9-ff2965979cf3 Video recording] | ||
Latest revision as of 22:15, 28 July 2023
- Speaker(s): Tristan Gingold
- email: Tristan Gingold
Downloads
Abstract
GHDL was first a compiled VHDL simulator. It was later extended to support synthesis, either standalone and generating a simple vhdl or verilog netlist), or as a plugin for yosys. Recently a limited support of verilog has been added in order to improve the support of mixed-language design synthesis. The rules to mix designs are discussed in this presentation.
Software
General information
- Repository: https://github.com/ghdl/ghdl
- Main documentation website: https://github.com/ghdl/ghdl
Roadmap
- The project seeks help on: AMS