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  • Open (and Closed) Source Analog Design with Hdl21 & VLSIR
    * Speaker(s): Dan Fritchman * Hdl21 - Analog HDL in Python - https://github.com/dan-fritchman/Hdl21
    847 bytes (123 words) - 22:26, 28 July 2023
  • FSiC2023
    * 9:30-10:00, Dan Fritchman (UC Berkeley), ''[[Open (and Closed) Source Analog Design with Hdl21 & VLSI
    13 KB (1,775 words) - 17:08, 1 October 2023
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