Moving toward VexiiRiscv

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  • Speaker: Charles Papon
  • email: charles.papon.90@gmail.com

Downloads

  • Slides (to upload a file: go to Edit mode, then click on the fourth icon from the left "Images and media" and follow the instructions)

Abstract

There is still very few free/open-source/multiple issue/in-order RISC-V CPU in the wild. In the same time, VexRiscv accumulated quite some technical debt and limitations. So it was time to fill those gaps !

VexiiRiscv aim at : - Providing a free/open-source CPU which can scale from simple micro controller, up to linux ready multi-issue core - Covering both 32 bits and 64 bits RISC-V + IMAFDC + B - Being Debian capable - Being very modular and extendable

This talk should normaly run on the hardware itself, minus kernel panics.

Hardware

General information


Roadmap