Difference between revisions of "Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana"

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(Created page with "* Speaker(s): Xxx Yyy * email: xx@yy.zz (voluntary information -it will help others to contact you in case of need) * other information: xxx ==Downloads== * :File:File_name...")
 
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* Speaker(s): Xxx Yyy
* Speaker(s): Thomas Benz
* email: xx@yy.zz (voluntary information -it will help others to contact you in case of need)
* email: tbenz@iis.ee.ethz.ch
* other information: xxx
* other information: PhD student at IIS, ETH Zurich - Member of the PULP group


==Downloads==
==Downloads==
* [[:File:File_name.pdf|Slides]] (to upload a file: go to Edit mode, then click on the fourth icon from the left "Embed file" and follow the instructions)
* [[https://iis-nextcloud.ee.ethz.ch/s/8eYtyij2oiMYbZo|Slides]]


==Abstract==
==Abstract==
Lorem Ipsum<ref>E. Miller, ''The history of Lorem Ipsum'', (New York: Academic Press, 2005), 23-5.</ref> is simply dummy text of the printing and typesetting industry. Lorem Ipsum has been the industry's standard dummy text ever since the 1500s, when an unknown printer took a galley of type and scrambled it to make a type specimen book. It has survived not only five centuries, but also the leap into electronic typesetting, remaining essentially unchanged. It was popularised in the 1960s with the release of Letraset sheets containing Lorem Ipsum passages, and more recently with desktop publishing software like Aldus PageMaker including versions of Lorem Ipsum.<ref>R. Smith, "Dummy text repositories", ''Scientific American'', 46 (April 1978): 44-6.</ref>
Recent advancements in FOSS EDA tools and the trend towards opening PDKs have enabled fully free and open-source ASIC design. However, open tools still lack feature completeness compared to their commercial counterparts, particularly in their support for SystemVerilog. Despite the emergence of alternative HDL languages and HLS approaches, many commercial and open-source IPs are still written in SystemVerilog.
 
In this talk, we discuss our experience synthesizing Iguana, the first end-to-end FOS Linux-capable ASIC.  
We encounter challenges with SystemVerilog support of our IPs in various open tools as proper processing of many of the language constructs requires full elaboration. To bridge important gaps in open frontend flows, we develop SVase, our own SystemVerilog pre-elaborator and simplifier based on the best-in-class Slang library. We present the technical details of SVase and its place in the synthesis flow of Iguana.  
Furthermore, we discuss the quality of results obtained from synthesizing Iguana with Yosys. Particularly two reasons for a significant increase in the area and the critical path in some modules of the design.


==Software==
==Software==
===General information===
===General information===
* Repository: https://xxxx.yyy
* Repository:  
* Main documentation website: https://xxxx.yyy
* https://github.com/pulp-platform/iguana (we are in the process of releasing Iguana, which will be online during the next few weeks)
* Wikipedia page if any: https://en.wikipedia.org/wiki/XXX-YYY-ZZZ (if a Wikipedia article does not exist yet, please consider creating one).
* https://github.com/pulp-platform/svase
* The software has been used in the following projects: XXX, YYY, ZZZ


===Roadmap===
===Roadmap===
* The software wishes to interface with the following tools: XXX, YYY
* The project seeks help on:
* The project seeks help on: XXX, YYY
* Improving SVase to simplify more constructs no longer requiring SV2V
* Improving the generic mapping and part select implementation of Yosys
* Using slang directly to read in SystemVerilog into Yosys 


==References==
==References==
<references />
<references />

Revision as of 16:47, 7 July 2023

  • Speaker(s): Thomas Benz
  • email: tbenz@iis.ee.ethz.ch
  • other information: PhD student at IIS, ETH Zurich - Member of the PULP group

Downloads

Abstract

Recent advancements in FOSS EDA tools and the trend towards opening PDKs have enabled fully free and open-source ASIC design. However, open tools still lack feature completeness compared to their commercial counterparts, particularly in their support for SystemVerilog. Despite the emergence of alternative HDL languages and HLS approaches, many commercial and open-source IPs are still written in SystemVerilog.

In this talk, we discuss our experience synthesizing Iguana, the first end-to-end FOS Linux-capable ASIC. We encounter challenges with SystemVerilog support of our IPs in various open tools as proper processing of many of the language constructs requires full elaboration. To bridge important gaps in open frontend flows, we develop SVase, our own SystemVerilog pre-elaborator and simplifier based on the best-in-class Slang library. We present the technical details of SVase and its place in the synthesis flow of Iguana. Furthermore, we discuss the quality of results obtained from synthesizing Iguana with Yosys. Particularly two reasons for a significant increase in the area and the critical path in some modules of the design.

Software

General information

  • Repository:
* https://github.com/pulp-platform/iguana (we are in the process of releasing Iguana, which will be online during the next few weeks)
* https://github.com/pulp-platform/svase

Roadmap

  • The project seeks help on:
* Improving SVase to simplify more constructs no longer requiring SV2V
* Improving the generic mapping and part select implementation of Yosys
* Using slang directly to read in SystemVerilog into Yosys

References

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