Difference between revisions of "FSiC2024"
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== Tentative program == | == Tentative program == | ||
===High-level design and logic-synthesis=== | ===High-level design and logic-synthesis=== | ||
* Alessandro Tempia Calvino ([https://people.epfl.ch/alessandro.tempiacalvino/?lang=en EPFL]), ''[[The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies]]'' | |||
* Tristan Gingold ([http://ghdl.free.fr/ GHDL]), ''[[How to debug a simulation (tentative)]]'' | |||
* Charles Papon ([https://github.com/SpinalHDL SpinalHDL]), ''[[Moving toward VexiiRiscv]]'' | |||
* Martijn Bastiaan and Lucas ([https://qbaylogic.com Qbaylogic]), ''[[It's nice to have a choice: using Haskell for circuit design]]'' | |||
* Rajit Manohar ([https://yale.edu Yale]), ''[[The ACT EDA flow for asynchronous logic]]'' | |||
===Foundries and PDKs=== | ===Foundries and PDKs=== | ||
* Rene Scholz, Sergei Andreev, Krzysztof Herman ([https://www.ihp-microelectronics.com IHP Microelectronics]), ''[[Update on IHP open source PDK initiative & how to submit free open source designs in IHP technology]]'' | |||
* Sergei Andreev, T. Zecha, Krzysztof Herman ([https://www.ihp-microelectronics.com IHP Microelectronics]), ''[[IHP open source PDK: KLayout Pycell Development status]]'' | |||
* Joaquin Matres Abril (Google), ''[[Revolutionize your chip design with GDSFactory and Open Source PDKs]]'' | |||
===On-going FOS silicon projects=== | ===On-going FOS silicon projects=== | ||
* Xianjun Jiao ([https://github.com/open-sdr IMEC, OpenWiFi project]), ''[[An opensource Wi-Fi chip, What, Why and How? ]]'' | |||
* Matthew Venn ([https://www.yosyshq.com/ YosysHQ], [https://www.chipflow.io/ ChipFlow]), ''[[To be announced]]'' | |||
===Hardware security=== | ===Hardware security=== | ||
=== | * Dorian Bachelot ([https://www.degate.org/ Degate]), ''[[Degate: The stakes and challenges of silicon reverse engineering]]'' | ||
=== | |||
=== | ===Analog flow, transistor modelling and circuit simulation=== | ||
* Tim Edwards ([http://opencircuitdesign.com/ Open Circuit Design]), ''[[CACE: Defining an open-source analog and mixed-signal design flow]]'' | |||
* Felix Salfelder ([https://nlnet.nl/project/Gnucap-MixedSignals/ Gnucap MixedSignals]), ''[[Verilog-AMS in Gnucap (2024)|Verilog-AMS in Gnucap]]'' | |||
* Arpad Buermen ([https://fides.fe.uni-lj.si/~arpadb/cv/cv2024.pdf University of Ljubljana]), ''[[VASE: a Verilog-A Simulation Engine]]'' | |||
* Pepijn de Vos ([https://cedar-eda.com/ CedarEDA]), ''[[CedarEDA for open source silicon]]'' | |||
===Policy, EU projects and funding opportunities=== | |||
* Korbinian Schreiber and Tina Tauchnitz ([https://vdivde-it.de VDI/VDE-IT]), ''[[title to be announced]]'' | |||
* Luca Pezzarossa ([https://orbit.dtu.dk/en/persons/luca-pezzarossa DTU]), ''[[Introduction to the Chips JU project RIBL]]'' | |||
===Standards=== | |||
* Philippe Morey-Chaisemartin ([https://xyalis.com/ Xyalis]), ''[[The OASIS layout file format (tentative)]]'' | |||
===Back-end design tools=== | ===Back-end design tools=== | ||
* Andrew Kahng ([https://openroadinitiative.org/ OpenROAD Initiative]), ''[[The OpenROAD Initiative (tentative)]]'' | |||
* Christophe Alexandre ([https://github.com/xtofalex/naja Naja]), ''[[naja_edit, an open Source tool built on top of Naja (tentative)]]'' | |||
* Juhani Kataja ([https://www.csc.fi/home CSC]), ''[[Simulating electromagnetics with ElmerFEM]]'' | |||
* Mohamed Gaber ([https://github.com/AUCOHL/Fault Fault]), ''[[Fault, Open-Source EDA's Missing DFT Toolchain]]'' | |||
* Gabriel Gouvine ([http://lip6.fr/ LIP6]), ''[[Quaigh: open source test pattern generation]]'' | |||
* Andreas Krinke ([https://www.ifte.de/english/staff/krinke.html TU Dresden]), ''[[Generating DRC Runsets for IHP's OpenPDK - Lessons Learned]]'' | |||
* Dario Quintero ([https://piel.readthedocs.io/en/latest/sections/microservices/index.html PIEL]), ''[[Integrating Mixed-Signal Microelectronics and Photonics: A Co-Design Approach with Piel]]'' | |||
===Sustainability=== | ===Sustainability=== | ||
This session is organized independently by Sorbonne Université. The program and the submission instructions are available [https://largo.lip6.fr/en/events/ here]. | This session is organized independently by Sorbonne Université. The program and the submission instructions are available [https://largo.lip6.fr/en/events/ here]. | ||
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==Academic sponsors== | ==Academic sponsors== | ||
[[File:SUS_LIP6_CNRSnew.jpg|500px|link=https://www.lip6.fr]] | [[File:SUS_LIP6_CNRSnew.jpg|500px|link=https://www.lip6.fr]] | ||
[[File:irill.png|300px|link=https://www.irill.org]] | |||
[[File:cemip-logo.png|250px|link=https://sciences.sorbonne-universite.fr/faculte/ufr-instituts-observatoires-ecoles/ufr-dingenierie/plateformes-ingenierie/le-cemip-centre]] | |||
==Acknowledgements== | ==Acknowledgements== | ||
Revision as of 22:53, 4 April 2024
| Free Silicon Conference 2024 | |
|---|---|
 | |
| Genre | Free software and free hardware development conference |
| Location(s) | Paris, Sorbonne Université |
| Country | France |
| Website | wiki.f-si.org/index.php/FSiC2024 |
The 2024 Free Silicon Conference (FSiC) will take place in Paris (Sorbonne) on June 19, 20, 21 2024 (Wednesday to Friday). This event will build on top of the past FSiC editions. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere.
News
January 15: submissions are open.
Submission
For proposing a talk, please submit a title and a short summary at fsic2024 'at' f-si.org by May 1st. Topics are not restricted to the tentative program.
Participation
Participation to the conference is free of charge but the attendance must be reserved per email at fsic2024 'at' f-si.org. Details will be announced on this page and over the mastodon channel.
Organizing committee
‟Technology is political. I stand for defending free access to technology and the right for transparency.”
‟Free and transparent technology empowers people and protects fundamental freedoms.”
Constantin Gierczak-Galle
Student and enthousiast
‟Technology can be both Mankind's development and demise. Promoting the former while hindering the latter can only happen through decentralization, democratization and open collaboration.”
‟I am passionate about helping people with my technical skills. Coding EDA is like gardening to me: may it grow and feed people.”
‟I like to understand technology, to adapt and enhance it. Technology should not be mythical or owned by experts only, it needs to be comprehensible.”
Tentative program
High-level design and logic-synthesis
- Alessandro Tempia Calvino (EPFL), The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies
- Tristan Gingold (GHDL), How to debug a simulation (tentative)
- Charles Papon (SpinalHDL), Moving toward VexiiRiscv
- Martijn Bastiaan and Lucas (Qbaylogic), It's nice to have a choice: using Haskell for circuit design
- Rajit Manohar (Yale), The ACT EDA flow for asynchronous logic
Foundries and PDKs
- Rene Scholz, Sergei Andreev, Krzysztof Herman (IHP Microelectronics), Update on IHP open source PDK initiative & how to submit free open source designs in IHP technology
- Sergei Andreev, T. Zecha, Krzysztof Herman (IHP Microelectronics), IHP open source PDK: KLayout Pycell Development status
- Joaquin Matres Abril (Google), Revolutionize your chip design with GDSFactory and Open Source PDKs
On-going FOS silicon projects
- Xianjun Jiao (IMEC, OpenWiFi project), An opensource Wi-Fi chip, What, Why and How?
- Matthew Venn (YosysHQ, ChipFlow), To be announced
Hardware security
- Dorian Bachelot (Degate), Degate: The stakes and challenges of silicon reverse engineering
Analog flow, transistor modelling and circuit simulation
- Tim Edwards (Open Circuit Design), CACE: Defining an open-source analog and mixed-signal design flow
- Felix Salfelder (Gnucap MixedSignals), Verilog-AMS in Gnucap
- Arpad Buermen (University of Ljubljana), VASE: a Verilog-A Simulation Engine
- Pepijn de Vos (CedarEDA), CedarEDA for open source silicon
Policy, EU projects and funding opportunities
- Korbinian Schreiber and Tina Tauchnitz (VDI/VDE-IT), title to be announced
- Luca Pezzarossa (DTU), Introduction to the Chips JU project RIBL
Standards
- Philippe Morey-Chaisemartin (Xyalis), The OASIS layout file format (tentative)
Back-end design tools
- Andrew Kahng (OpenROAD Initiative), The OpenROAD Initiative (tentative)
- Christophe Alexandre (Naja), naja_edit, an open Source tool built on top of Naja (tentative)
- Juhani Kataja (CSC), Simulating electromagnetics with ElmerFEM
- Mohamed Gaber (Fault), Fault, Open-Source EDA's Missing DFT Toolchain
- Gabriel Gouvine (LIP6), Quaigh: open source test pattern generation
- Andreas Krinke (TU Dresden), Generating DRC Runsets for IHP's OpenPDK - Lessons Learned
- Dario Quintero (PIEL), Integrating Mixed-Signal Microelectronics and Photonics: A Co-Design Approach with Piel
Sustainability
This session is organized independently by Sorbonne Université. The program and the submission instructions are available here.
Local hosting committee
The event is hosted by Sorbonne Université (SU) and members of the LIP6 laboratory including Cécile Braunstein, Roselyne Chotin, Marie-Minerve Louerat and Franck Wajsbürt.
Donations
We are looking for sponsors to cover extra services at the conference, such as food and beverages. In case of interest, please write at fsic2024 'at' f-si.org.
Academic sponsors
Acknowledgements
This conference is funded by the EU HORIZON Coordination and Support Action GoIT project with ID number 101070669.
