A progressive introduction to memory bus interconnect API in Software-Defined Hardware
- Speaker(s): Charles Papon
- email: email@example.com
- other information: Dolu1990 (Github)
This talk will introduce differents API and paradigmes which can be used to specify an interconnect in software-defined hardware.
It will do so by showing some regular interconnects from the SpinalHDL library, before diving in some recent developpment mixing Tilelink, parameter negotiation, Multithreaded and decentralized hardware elaboration.
- Repository: https://github.com/SpinalHDL/SpinalHDL/tree/tilelink
- Open discussion: https://github.com/SpinalHDL/SpinalHDL/discussions/1115
- Tilelink infrastructure with memory coherency (With and without L2)
- SMP SoC with NaxRiscv