Difference between revisions of "A progressive introduction to memory bus interconnect API in Software-Defined Hardware"

From F-Si wiki
Jump to navigation Jump to search
(Created page with "* Speaker(s): Charles Papon * email: charles.papon.90@gmail.com * other information: Dolu1990 (Github) ==Downloads== * [https://github.com/SpinalHDL/SpinalDoc/blob/master/pre...")
 
 
Line 4: Line 4:


==Downloads==
==Downloads==
* [https://github.com/SpinalHDL/SpinalDoc/blob/master/presentation/en/fsic_100723/fsic_100723.pdf Slides]  
* [https://github.com/SpinalHDL/SpinalDoc/blob/master/presentation/en/fsic_100723/fsic_100723.pdf Slides]
* [https://peertube.f-si.org/videos/watch/bcf49c84-d21d-4571-a73e-96d7eb89e907 Video recording]


==Abstract==
==Abstract==

Latest revision as of 22:14, 28 July 2023

  • Speaker(s): Charles Papon
  • email: charles.papon.90@gmail.com
  • other information: Dolu1990 (Github)

Downloads

Abstract

This talk will introduce differents API and paradigmes which can be used to specify an interconnect in software-defined hardware.

It will do so by showing some regular interconnects from the SpinalHDL library, before diving in some recent developpment mixing Tilelink, parameter negotiation, Multithreaded and decentralized hardware elaboration.

Software

General information

Roadmap

  • Tilelink infrastructure with memory coherency (With and without L2)
  • SMP SoC with NaxRiscv
Retrieved from "https://wiki.f-si.org/index.php?title=A_progressive_introduction_to_memory_bus_interconnect_API_in_Software-Defined_Hardware&oldid=3047"