Difference between revisions of "Moving toward VexiiRiscv"
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==Downloads== | ==Downloads== | ||
* | * [https://github.com/SpinalHDL/SpinalDoc/tree/master/presentation/en/fsic_2024 Slides] | ||
* | * [https://peertube6.f-si.org/w/6sTipzg5dy8Ya83gNjLvrN Video recording] | ||
==Abstract== | ==Abstract== | ||
Latest revision as of 15:32, 1 August 2024
- Speaker: Charles Papon
- email: charles.papon.90@gmail.com
Downloads
Abstract
There is still very few free/open-source/multiple issue/in-order RISC-V CPU in the wild. In the same time, VexRiscv accumulated quite some technical debt and limitations. So it was time to fill those gaps !
VexiiRiscv aim at :
- Providing a free/open-source CPU which can scale from simple micro controller, up to linux ready multi-core / multi-issue cluster (Cortex A53/A55 like)
- Covering both 32 bits and 64 bits RISC-V + IMAFDC + B
- Being very modular and extendable
- Being Debian capable
This talk should normaly run on the hardware itself (FPGA), minus maybe, some kernel panics.
Hardware
General information
- Repository: https://github.com/SpinalHDL/VexiiRiscv
- Main documentation website: https://spinalhdl.github.io/VexiiRiscv-RTD/master/index.html
Roadmap
- The project seeks help on: https://github.com/SpinalHDL/VexiiRiscv/issues/1